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90 | 90 | #define LVTS_GOLDEN_TEMP_DEFAULT 50 |
91 | 91 | #define LVTS_COEFF_A_MT8195 -250460 |
92 | 92 | #define LVTS_COEFF_B_MT8195 250460 |
| 93 | +#define LVTS_COEFF_A_MT7987 -204650 |
| 94 | +#define LVTS_COEFF_B_MT7987 204650 |
93 | 95 | #define LVTS_COEFF_A_MT7988 -204650 |
94 | 96 | #define LVTS_COEFF_B_MT7988 204650 |
95 | 97 | #define LVTS_COEFF_A_MT8196 391460 |
@@ -1507,6 +1509,20 @@ static void lvts_remove(struct platform_device *pdev) |
1507 | 1509 | lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], false); |
1508 | 1510 | } |
1509 | 1511 |
|
| 1512 | +static const struct lvts_ctrl_data mt7987_lvts_ap_data_ctrl[] = { |
| 1513 | + { |
| 1514 | + .lvts_sensor = { |
| 1515 | + { .dt_id = MT7987_CPU, |
| 1516 | + .cal_offsets = { 0x04, 0x05, 0x06 } }, |
| 1517 | + { .dt_id = MT7987_ETH2P5G, |
| 1518 | + .cal_offsets = { 0x08, 0x09, 0x0a } }, |
| 1519 | + }, |
| 1520 | + VALID_SENSOR_MAP(1, 1, 0, 0), |
| 1521 | + .offset = 0x0, |
| 1522 | + .mode = LVTS_MSR_FILTERED_MODE, |
| 1523 | + }, |
| 1524 | +}; |
| 1525 | + |
1510 | 1526 | static const struct lvts_ctrl_data mt7988_lvts_ap_data_ctrl[] = { |
1511 | 1527 | { |
1512 | 1528 | .lvts_sensor = { |
@@ -1589,6 +1605,12 @@ static const u32 default_init_cmds[] = { |
1589 | 1605 | 0xC10300FC, 0xC103009D, 0xC10300F1, 0xC10300E1 |
1590 | 1606 | }; |
1591 | 1607 |
|
| 1608 | +static const u32 mt7987_init_cmds[] = { |
| 1609 | + 0xC1030300, 0xC1030420, 0xC1030500, 0xC10307A6, 0xC10308C7, |
| 1610 | + 0xC103098D, 0xC1030C7C, 0xC1030AA8, 0xC10308CE, 0xC10308C7, |
| 1611 | + 0xC1030B04, 0xC1030E01, 0xC10306B8 |
| 1612 | +}; |
| 1613 | + |
1592 | 1614 | static const u32 mt7988_init_cmds[] = { |
1593 | 1615 | 0xC1030300, 0xC1030420, 0xC1030500, 0xC10307A6, 0xC1030CFC, |
1594 | 1616 | 0xC1030A8C, 0xC103098D, 0xC10308F1, 0xC1030B04, 0xC1030E01, |
@@ -1993,6 +2015,19 @@ static const struct lvts_platform_ops lvts_platform_ops_mt8196 = { |
1993 | 2015 | .lvts_temp_to_raw = lvts_temp_to_raw_mt8196, |
1994 | 2016 | }; |
1995 | 2017 |
|
| 2018 | +static const struct lvts_data mt7987_lvts_ap_data = { |
| 2019 | + .lvts_ctrl = mt7987_lvts_ap_data_ctrl, |
| 2020 | + .num_lvts_ctrl = ARRAY_SIZE(mt7987_lvts_ap_data_ctrl), |
| 2021 | + .conn_cmd = mt7988_conn_cmds, |
| 2022 | + .init_cmd = mt7987_init_cmds, |
| 2023 | + .num_conn_cmd = ARRAY_SIZE(mt7988_conn_cmds), |
| 2024 | + .num_init_cmd = ARRAY_SIZE(mt7987_init_cmds), |
| 2025 | + .temp_factor = LVTS_COEFF_A_MT7987, |
| 2026 | + .temp_offset = LVTS_COEFF_B_MT7987, |
| 2027 | + .gt_calib_bit_offset = 32, |
| 2028 | + .def_calibration = 19380, |
| 2029 | +}; |
| 2030 | + |
1996 | 2031 | static const struct lvts_data mt7988_lvts_ap_data = { |
1997 | 2032 | .lvts_ctrl = mt7988_lvts_ap_data_ctrl, |
1998 | 2033 | .conn_cmd = mt7988_conn_cmds, |
@@ -2137,6 +2172,7 @@ static const struct lvts_data mt8196_lvts_ap_data = { |
2137 | 2172 | }; |
2138 | 2173 |
|
2139 | 2174 | static const struct of_device_id lvts_of_match[] = { |
| 2175 | + { .compatible = "mediatek,mt7987-lvts-ap", .data = &mt7987_lvts_ap_data }, |
2140 | 2176 | { .compatible = "mediatek,mt7988-lvts-ap", .data = &mt7988_lvts_ap_data }, |
2141 | 2177 | { .compatible = "mediatek,mt8186-lvts", .data = &mt8186_lvts_data }, |
2142 | 2178 | { .compatible = "mediatek,mt8188-lvts-mcu", .data = &mt8188_lvts_mcu_data }, |
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