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Merge tag 'renesas-clk-for-v5.12-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull Renesas clk driver updates from Geert Uytterhoeven: - Add I2c and Ethernet (RAVB) clocks on R-Car V3U - Fix a kerneldoc issue - Add timer (TMU) clocks on most R-Car Gen3 SoCs - Add video-related (FCPVD/VSPD/VSPX), watchdog (RWDT), serial (HSCIF), pincontrol/GPIO (PFC/GPIO), SPI (MSIOF), SDHI, and DMA (SYS-DMAC) clocks on R-Car V3U - Add support for the USB 2.0 clock selector on RZ/G2 SoCs - Minor fixes and improvements * tag 'renesas-clk-for-v5.12-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: (21 commits) clk: renesas: cpg-mssr: Fix formatting issues for 'smstpcr_saved's documentation clk: renesas: r8a779a0: Add RAVB clocks clk: renesas: r8a779a0: Add I2C clocks dt-bindings: clock: renesas: rcar-usb2-clock-sel: Add support for RZ/G2 M/N/H clk: renesas: r8a779a0: Add SYS-DMAC clocks clk: renesas: r8a779a0: Add SDHI support clk: renesas: rcar-gen3: Factor out CPG library clk: renesas: rcar-gen3: Remove cpg_quirks access when registering SD clock clk: renesas: r8a779a0: Add MSIOF clocks clk: renesas: r8a779a0: Add PFC/GPIO clocks clk: renesas: r8a779a0: Fix parent of CBFUSA clock clk: renesas: r8a779a0: Remove non-existent S2 clock clk: renesas: r8a779a0: Add HSCIF support clk: renesas: r8a779a0: Add RWDT clocks clk: renesas: r8a779a0: Add VSPX clock support clk: renesas: r8a779a0: Add VSPD clock support clk: renesas: r8a779a0: Add FCPVD clock support clk: renesas: r8a77995: Add TMU clocks clk: renesas: r8a77990: Add TMU clocks clk: renesas: r8a77965: Add TMU clocks ...
2 parents 5c8fe58 + 24ece96 commit 7907e69

12 files changed

Lines changed: 406 additions & 264 deletions

File tree

‎Documentation/devicetree/bindings/clock/renesas,rcar-usb2-clock-sel.yaml‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -35,6 +35,9 @@ properties:
3535
compatible:
3636
items:
3737
- enum:
38+
- renesas,r8a774a1-rcar-usb2-clock-sel # RZ/G2M
39+
- renesas,r8a774b1-rcar-usb2-clock-sel # RZ/G2N
40+
- renesas,r8a774e1-rcar-usb2-clock-sel # RZ/G2H
3841
- renesas,r8a7795-rcar-usb2-clock-sel # R-Car H3
3942
- renesas,r8a7796-rcar-usb2-clock-sel # R-Car M3-W
4043
- renesas,r8a77961-rcar-usb2-clock-sel # R-Car M3-W+

‎drivers/clk/renesas/Kconfig‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -148,6 +148,7 @@ config CLK_R8A77995
148148

149149
config CLK_R8A779A0
150150
bool "R-Car V3U clock support" if COMPILE_TEST
151+
select CLK_RCAR_CPG_LIB
151152
select CLK_RENESAS_CPG_MSSR
152153

153154
config CLK_R9A06G032
@@ -162,12 +163,16 @@ config CLK_SH73A0
162163

163164

164165
# Family
166+
config CLK_RCAR_CPG_LIB
167+
bool "CPG/MSSR library functions" if COMPILE_TEST
168+
165169
config CLK_RCAR_GEN2_CPG
166170
bool "R-Car Gen2 CPG clock support" if COMPILE_TEST
167171
select CLK_RENESAS_CPG_MSSR
168172

169173
config CLK_RCAR_GEN3_CPG
170174
bool "R-Car Gen3 and RZ/G2 CPG clock support" if COMPILE_TEST
175+
select CLK_RCAR_CPG_LIB
171176
select CLK_RENESAS_CPG_MSSR
172177

173178
config CLK_RCAR_USB2_CLOCK_SEL

‎drivers/clk/renesas/Makefile‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -32,6 +32,7 @@ obj-$(CONFIG_CLK_R9A06G032) += r9a06g032-clocks.o
3232
obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o
3333

3434
# Family
35+
obj-$(CONFIG_CLK_RCAR_CPG_LIB) += rcar-cpg-lib.o
3536
obj-$(CONFIG_CLK_RCAR_GEN2_CPG) += rcar-gen2-cpg.o
3637
obj-$(CONFIG_CLK_RCAR_GEN3_CPG) += rcar-gen3-cpg.o
3738
obj-$(CONFIG_CLK_RCAR_USB2_CLOCK_SEL) += rcar-usb2-clock-sel.o

‎drivers/clk/renesas/r8a7796-cpg-mssr.c‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -128,6 +128,11 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = {
128128

129129
static struct mssr_mod_clk r8a7796_mod_clks[] __initdata = {
130130
DEF_MOD("fdp1-0", 119, R8A7796_CLK_S0D1),
131+
DEF_MOD("tmu4", 121, R8A7796_CLK_S0D6),
132+
DEF_MOD("tmu3", 122, R8A7796_CLK_S3D2),
133+
DEF_MOD("tmu2", 123, R8A7796_CLK_S3D2),
134+
DEF_MOD("tmu1", 124, R8A7796_CLK_S3D2),
135+
DEF_MOD("tmu0", 125, R8A7796_CLK_CP),
131136
DEF_MOD("scif5", 202, R8A7796_CLK_S3D4),
132137
DEF_MOD("scif4", 203, R8A7796_CLK_S3D4),
133138
DEF_MOD("scif3", 204, R8A7796_CLK_S3D4),

‎drivers/clk/renesas/r8a77965-cpg-mssr.c‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -123,6 +123,11 @@ static const struct cpg_core_clk r8a77965_core_clks[] __initconst = {
123123

124124
static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = {
125125
DEF_MOD("fdp1-0", 119, R8A77965_CLK_S0D1),
126+
DEF_MOD("tmu4", 121, R8A77965_CLK_S0D6),
127+
DEF_MOD("tmu3", 122, R8A77965_CLK_S3D2),
128+
DEF_MOD("tmu2", 123, R8A77965_CLK_S3D2),
129+
DEF_MOD("tmu1", 124, R8A77965_CLK_S3D2),
130+
DEF_MOD("tmu0", 125, R8A77965_CLK_CP),
126131
DEF_MOD("scif5", 202, R8A77965_CLK_S3D4),
127132
DEF_MOD("scif4", 203, R8A77965_CLK_S3D4),
128133
DEF_MOD("scif3", 204, R8A77965_CLK_S3D4),

‎drivers/clk/renesas/r8a77990-cpg-mssr.c‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -124,6 +124,11 @@ static const struct cpg_core_clk r8a77990_core_clks[] __initconst = {
124124
};
125125

126126
static const struct mssr_mod_clk r8a77990_mod_clks[] __initconst = {
127+
DEF_MOD("tmu4", 121, R8A77990_CLK_S0D6C),
128+
DEF_MOD("tmu3", 122, R8A77990_CLK_S3D2C),
129+
DEF_MOD("tmu2", 123, R8A77990_CLK_S3D2C),
130+
DEF_MOD("tmu1", 124, R8A77990_CLK_S3D2C),
131+
DEF_MOD("tmu0", 125, R8A77990_CLK_CP),
127132
DEF_MOD("scif5", 202, R8A77990_CLK_S3D4C),
128133
DEF_MOD("scif4", 203, R8A77990_CLK_S3D4C),
129134
DEF_MOD("scif3", 204, R8A77990_CLK_S3D4C),

‎drivers/clk/renesas/r8a77995-cpg-mssr.c‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -111,6 +111,11 @@ static const struct cpg_core_clk r8a77995_core_clks[] __initconst = {
111111
};
112112

113113
static const struct mssr_mod_clk r8a77995_mod_clks[] __initconst = {
114+
DEF_MOD("tmu4", 121, R8A77995_CLK_S1D4C),
115+
DEF_MOD("tmu3", 122, R8A77995_CLK_S3D2C),
116+
DEF_MOD("tmu2", 123, R8A77995_CLK_S3D2C),
117+
DEF_MOD("tmu1", 124, R8A77995_CLK_S3D2C),
118+
DEF_MOD("tmu0", 125, R8A77995_CLK_CP),
114119
DEF_MOD("scif5", 202, R8A77995_CLK_S3D4C),
115120
DEF_MOD("scif4", 203, R8A77995_CLK_S3D4C),
116121
DEF_MOD("scif3", 204, R8A77995_CLK_S3D4C),

‎drivers/clk/renesas/r8a779a0-cpg-mssr.c‎

Lines changed: 63 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -25,13 +25,15 @@
2525

2626
#include <dt-bindings/clock/r8a779a0-cpg-mssr.h>
2727

28+
#include "rcar-cpg-lib.h"
2829
#include "renesas-cpg-mssr.h"
2930

3031
enum rcar_r8a779a0_clk_types {
3132
CLK_TYPE_R8A779A0_MAIN = CLK_TYPE_CUSTOM,
3233
CLK_TYPE_R8A779A0_PLL1,
3334
CLK_TYPE_R8A779A0_PLL2X_3X, /* PLL[23][01] */
3435
CLK_TYPE_R8A779A0_PLL5,
36+
CLK_TYPE_R8A779A0_SD,
3537
CLK_TYPE_R8A779A0_MDSEL, /* Select parent/divider using mode pin */
3638
CLK_TYPE_R8A779A0_OSC, /* OSC EXTAL predivider and fixed divider */
3739
};
@@ -69,7 +71,6 @@ enum clk_ids {
6971
CLK_PLL5_DIV2,
7072
CLK_PLL5_DIV4,
7173
CLK_S1,
72-
CLK_S2,
7374
CLK_S3,
7475
CLK_SDSRC,
7576
CLK_RPCSRC,
@@ -83,6 +84,9 @@ enum clk_ids {
8384
DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_PLL2X_3X, CLK_MAIN, \
8485
.offset = _offset)
8586

87+
#define DEF_SD(_name, _id, _parent, _offset) \
88+
DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_SD, _parent, .offset = _offset)
89+
8690
#define DEF_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \
8791
DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_MDSEL, \
8892
(_parent0) << 16 | (_parent1), \
@@ -114,6 +118,7 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
114118
DEF_FIXED(".pll5_div4", CLK_PLL5_DIV4, CLK_PLL5_DIV2, 2, 1),
115119
DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 2, 1),
116120
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 4, 1),
121+
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL5_DIV4, 1, 1),
117122
DEF_RATE(".oco", CLK_OCO, 32768),
118123

119124
/* Core Clock Outputs */
@@ -137,7 +142,10 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
137142
DEF_FIXED("icu", R8A779A0_CLK_ICU, CLK_PLL5_DIV4, 2, 1),
138143
DEF_FIXED("icud2", R8A779A0_CLK_ICUD2, CLK_PLL5_DIV4, 4, 1),
139144
DEF_FIXED("vcbus", R8A779A0_CLK_VCBUS, CLK_PLL5_DIV4, 1, 1),
140-
DEF_FIXED("cbfusa", R8A779A0_CLK_CBFUSA, CLK_MAIN, 2, 1),
145+
DEF_FIXED("cbfusa", R8A779A0_CLK_CBFUSA, CLK_EXTAL, 2, 1),
146+
DEF_FIXED("cp", R8A779A0_CLK_CP, CLK_EXTAL, 2, 1),
147+
148+
DEF_SD("sd0", R8A779A0_CLK_SD0, CLK_SDSRC, 0x870),
141149

142150
DEF_DIV6P1("mso", R8A779A0_CLK_MSO, CLK_PLL5_DIV4, 0x87c),
143151
DEF_DIV6P1("canfd", R8A779A0_CLK_CANFD, CLK_PLL5_DIV4, 0x878),
@@ -148,14 +156,42 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
148156
};
149157

150158
static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = {
159+
DEF_MOD("avb0", 211, R8A779A0_CLK_S3D2),
160+
DEF_MOD("avb1", 212, R8A779A0_CLK_S3D2),
161+
DEF_MOD("avb2", 213, R8A779A0_CLK_S3D2),
162+
DEF_MOD("avb3", 214, R8A779A0_CLK_S3D2),
163+
DEF_MOD("avb4", 215, R8A779A0_CLK_S3D2),
164+
DEF_MOD("avb5", 216, R8A779A0_CLK_S3D2),
151165
DEF_MOD("csi40", 331, R8A779A0_CLK_CSI0),
152166
DEF_MOD("csi41", 400, R8A779A0_CLK_CSI0),
153167
DEF_MOD("csi42", 401, R8A779A0_CLK_CSI0),
154168
DEF_MOD("csi43", 402, R8A779A0_CLK_CSI0),
169+
DEF_MOD("fcpvd0", 508, R8A779A0_CLK_S3D1),
170+
DEF_MOD("fcpvd1", 509, R8A779A0_CLK_S3D1),
171+
DEF_MOD("hscif0", 514, R8A779A0_CLK_S1D2),
172+
DEF_MOD("hscif1", 515, R8A779A0_CLK_S1D2),
173+
DEF_MOD("hscif2", 516, R8A779A0_CLK_S1D2),
174+
DEF_MOD("hscif3", 517, R8A779A0_CLK_S1D2),
175+
DEF_MOD("i2c0", 518, R8A779A0_CLK_S1D4),
176+
DEF_MOD("i2c1", 519, R8A779A0_CLK_S1D4),
177+
DEF_MOD("i2c2", 520, R8A779A0_CLK_S1D4),
178+
DEF_MOD("i2c3", 521, R8A779A0_CLK_S1D4),
179+
DEF_MOD("i2c4", 522, R8A779A0_CLK_S1D4),
180+
DEF_MOD("i2c5", 523, R8A779A0_CLK_S1D4),
181+
DEF_MOD("i2c6", 524, R8A779A0_CLK_S1D4),
182+
DEF_MOD("msi0", 618, R8A779A0_CLK_MSO),
183+
DEF_MOD("msi1", 619, R8A779A0_CLK_MSO),
184+
DEF_MOD("msi2", 620, R8A779A0_CLK_MSO),
185+
DEF_MOD("msi3", 621, R8A779A0_CLK_MSO),
186+
DEF_MOD("msi4", 622, R8A779A0_CLK_MSO),
187+
DEF_MOD("msi5", 623, R8A779A0_CLK_MSO),
155188
DEF_MOD("scif0", 702, R8A779A0_CLK_S1D8),
156189
DEF_MOD("scif1", 703, R8A779A0_CLK_S1D8),
157190
DEF_MOD("scif3", 704, R8A779A0_CLK_S1D8),
158191
DEF_MOD("scif4", 705, R8A779A0_CLK_S1D8),
192+
DEF_MOD("sdhi0", 706, R8A779A0_CLK_SD0),
193+
DEF_MOD("sydm1", 709, R8A779A0_CLK_S1D2),
194+
DEF_MOD("sydm2", 710, R8A779A0_CLK_S1D2),
159195
DEF_MOD("vin00", 730, R8A779A0_CLK_S1D1),
160196
DEF_MOD("vin01", 731, R8A779A0_CLK_S1D1),
161197
DEF_MOD("vin02", 800, R8A779A0_CLK_S1D1),
@@ -188,10 +224,19 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = {
188224
DEF_MOD("vin35", 827, R8A779A0_CLK_S1D1),
189225
DEF_MOD("vin36", 828, R8A779A0_CLK_S1D1),
190226
DEF_MOD("vin37", 829, R8A779A0_CLK_S1D1),
227+
DEF_MOD("vspd0", 830, R8A779A0_CLK_S3D1),
228+
DEF_MOD("vspd1", 831, R8A779A0_CLK_S3D1),
229+
DEF_MOD("rwdt", 907, R8A779A0_CLK_R),
230+
DEF_MOD("pfc0", 915, R8A779A0_CLK_CP),
231+
DEF_MOD("pfc1", 916, R8A779A0_CLK_CP),
232+
DEF_MOD("pfc2", 917, R8A779A0_CLK_CP),
233+
DEF_MOD("pfc3", 918, R8A779A0_CLK_CP),
234+
DEF_MOD("vspx0", 1028, R8A779A0_CLK_S1D1),
235+
DEF_MOD("vspx1", 1029, R8A779A0_CLK_S1D1),
236+
DEF_MOD("vspx2", 1030, R8A779A0_CLK_S1D1),
237+
DEF_MOD("vspx3", 1031, R8A779A0_CLK_S1D1),
191238
};
192239

193-
static spinlock_t cpg_lock;
194-
195240
static const struct rcar_r8a779a0_cpg_pll_config *cpg_pll_config __initdata;
196241
static unsigned int cpg_clk_extalr __initdata;
197242
static u32 cpg_mode __initdata;
@@ -230,6 +275,12 @@ static struct clk * __init rcar_r8a779a0_cpg_clk_register(struct device *dev,
230275
div = cpg_pll_config->pll5_div;
231276
break;
232277

278+
case CLK_TYPE_R8A779A0_SD:
279+
return cpg_sd_clk_register(core->name, base, core->offset,
280+
__clk_get_name(parent), notifiers,
281+
false);
282+
break;
283+
233284
case CLK_TYPE_R8A779A0_MDSEL:
234285
/*
235286
* Clock selectable between two parents and two fixed dividers
@@ -261,6 +312,10 @@ static struct clk * __init rcar_r8a779a0_cpg_clk_register(struct device *dev,
261312
__clk_get_name(parent), 0, mult, div);
262313
}
263314

315+
static const unsigned int r8a779a0_crit_mod_clks[] __initconst = {
316+
MOD_CLK_ID(907), /* RWDT */
317+
};
318+
264319
/*
265320
* CPG Clock Data
266321
*/
@@ -311,6 +366,10 @@ const struct cpg_mssr_info r8a779a0_cpg_mssr_info __initconst = {
311366
.num_mod_clks = ARRAY_SIZE(r8a779a0_mod_clks),
312367
.num_hw_mod_clks = 15 * 32,
313368

369+
/* Critical Module Clocks */
370+
.crit_mod_clks = r8a779a0_crit_mod_clks,
371+
.num_crit_mod_clks = ARRAY_SIZE(r8a779a0_crit_mod_clks),
372+
314373
/* Callbacks */
315374
.init = r8a779a0_cpg_mssr_init,
316375
.cpg_clk_register = rcar_r8a779a0_cpg_clk_register,

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