Merge tag 'riscv-dt-for-v6.7' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt

RISC-V Devicetrees for v6.7

StarFive:
Things are a bit slower for StarFive this window, there's only the
addition of audio related DT nodes to speak of here.

Generic:
The SiFive, StarFive and Microchip devicetrees have had my replacement
ISA extension detection properties added. Unfortunately, the old
"riscv,isa" property never defined exactly what the extensions it
contained meant, and people were want to fill it in incorrectly (and
call upstream kernel devs idiots for not doing the same). The new
properties have explicit definitions and hopefully will stand up better
to some of the variation from RVI.

Sophgo:
Two new SoCs, one is probably the first of several with up/down tuned
variants, that have a pair of T-Head c906 cores and appear aimed at the
IP camera, smart <insert whatever> etc markets. They are intended to run
in AMP mode, with an RTOS on the less powerful core. The other is far
more interesting to kernel developers however, the 64-core SG2042, with
more recent c920 cores from T-Head at 2 GHz. For both, support is at a
very basic stage - some of the same developers are working on them as
other T-Head powered SoCs, but hopefully things will move beyond a basic
console boot. The goal is for Chen Wang to take over maintaining the
Sophgo support once they have some more experience with the process.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

* tag 'riscv-dt-for-v6.7' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: (22 commits)
  riscv: dts: starfive: convert isa detection to new properties
  riscv: dts: sifive: convert isa detection to new properties
  riscv: dts: microchip: convert isa detection to new properties
  riscv: dts: sophgo: add Milk-V Duo board device tree
  riscv: dts: sophgo: add initial CV1800B SoC device tree
  dt-bindings: riscv: Add Milk-V Duo board compatibles
  dt-bindings: timer: Add SOPHGO CV1800B clint
  dt-bindings: interrupt-controller: Add SOPHGO CV1800B plic
  riscv: defconfig: enable SOPHGO SoC
  riscv: dts: sophgo: add Milk-V Pioneer board device tree
  riscv: dts: add initial Sophgo SG2042 SoC device tree
  dt-bindings: interrupt-controller: Add Sophgo sg2042 CLINT mswi
  dt-bindings: timer: Add Sophgo sg2042 CLINT timer
  dt-bindings: interrupt-controller: Add Sophgo SG2042 PLIC
  dt-bindings: riscv: Add T-HEAD C920 compatibles
  dt-bindings: riscv: add sophgo sg2042 bindings
  dt-bindings: vendor-prefixes: add milkv/sophgo
  riscv: Add SOPHGO SOC family Kconfig support
  riscv: dts: starfive: add assigned-clock* to limit frquency
  riscv: dts: starfive: Add JH7110 PWM-DAC support
  ...

Link: https://lore.kernel.org/r/20231016-filing-payroll-7aca51b8f1a3@spud
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Author: arndb

Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml

@@ -65,6 +65,8 @@ properties:
       - items:
           - enum:
               - allwinner,sun20i-d1-plic
+              - sophgo,cv1800b-plic
+              - sophgo,sg2042-plic
               - thead,th1520-plic
           - const: thead,c900-plic
       - items:

Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-mswi.yaml

@@ -0,0 +1,43 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/thead,c900-aclint-mswi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sophgo sg2042 CLINT Machine-level Software Interrupt Device
+
+maintainers:
+  - Inochi Amaoto <inochiama@outlook.com>
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - sophgo,sg2042-aclint-mswi
+      - const: thead,c900-aclint-mswi
+
+  reg:
+    maxItems: 1
+
+  interrupts-extended:
+    minItems: 1
+    maxItems: 4095
+
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - interrupts-extended
+
+examples:
+  - |
+    interrupt-controller@94000000 {
+      compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi";
+      interrupts-extended = <&cpu1intc 3>,
+                            <&cpu2intc 3>,
+                            <&cpu3intc 3>,
+                            <&cpu4intc 3>;
+      reg = <0x94000000 0x00010000>;
+    };
+...

Documentation/devicetree/bindings/riscv/cpus.yaml

@@ -47,6 +47,7 @@ properties:
               - sifive,u74-mc
               - thead,c906
               - thead,c910
+              - thead,c920
           - const: riscv
       - items:
           - enum:

Documentation/devicetree/bindings/riscv/sophgo.yaml

@@ -0,0 +1,32 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/riscv/sophgo.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sophgo SoC-based boards
+
+maintainers:
+  - Chao Wei <chao.wei@sophgo.com>
+  - Chen Wang <unicorn_wang@outlook.com>
+
+description:
+  Sophgo SoC-based boards
+
+properties:
+  $nodename:
+    const: '/'
+  compatible:
+    oneOf:
+      - items:
+          - enum:
+              - milkv,duo
+          - const: sophgo,cv1800b
+      - items:
+          - enum:
+              - milkv,pioneer
+          - const: sophgo,sg2042
+
+additionalProperties: true
+
+...

Documentation/devicetree/bindings/timer/sifive,clint.yaml

@@ -37,6 +37,7 @@ properties:
       - items:
           - enum:
               - allwinner,sun20i-d1-clint
+              - sophgo,cv1800b-clint
               - thead,th1520-clint
           - const: thead,c900-clint
       - items:

Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml

@@ -0,0 +1,43 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/thead,c900-aclint-mtimer.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sophgo CLINT Timer
+
+maintainers:
+  - Inochi Amaoto <inochiama@outlook.com>
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - sophgo,sg2042-aclint-mtimer
+      - const: thead,c900-aclint-mtimer
+
+  reg:
+    maxItems: 1
+
+  interrupts-extended:
+    minItems: 1
+    maxItems: 4095
+
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - interrupts-extended
+
+examples:
+  - |
+    timer@ac000000 {
+      compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
+      interrupts-extended = <&cpu1intc 7>,
+                            <&cpu2intc 7>,
+                            <&cpu3intc 7>,
+                            <&cpu4intc 7>;
+      reg = <0xac000000 0x00010000>;
+    };
+...

Documentation/devicetree/bindings/vendor-prefixes.yaml

@@ -877,6 +877,8 @@ patternProperties:
     description: MikroElektronika d.o.o.
   "^mikrotik,.*":
     description: MikroTik
+  "^milkv,.*":
+    description: MilkV Technology Co., Ltd
   "^miniand,.*":
     description: Miniand Tech
   "^minix,.*":
@@ -1287,6 +1289,8 @@ patternProperties:
     description: Solomon Systech Limited
   "^sony,.*":
     description: Sony Corporation
+  "^sophgo,.*":
+    description: Sophgo Technology Inc.
   "^sourceparts,.*":
     description: Source Parts Inc.
   "^spansion,.*":

MAINTAINERS

@@ -20063,6 +20063,13 @@ F:	drivers/char/sonypi.c
 F:	drivers/platform/x86/sony-laptop.c
 F:	include/linux/sony-laptop.h
 
+SOPHGO DEVICETREES
+M:	Chao Wei <chao.wei@sophgo.com>
+M:	Chen Wang <unicorn_wang@outlook.com>
+S:	Maintained
+F:	arch/riscv/boot/dts/sophgo/
+F:	Documentation/devicetree/bindings/riscv/sophgo.yaml
+
 SOUND
 M:	Jaroslav Kysela <perex@perex.cz>
 M:	Takashi Iwai <tiwai@suse.com>

arch/riscv/Kconfig.socs

@@ -22,6 +22,11 @@ config SOC_SIFIVE
 	help
 	  This enables support for SiFive SoC platform hardware.
 
+config ARCH_SOPHGO
+	bool "Sophgo SoCs"
+	help
+	  This enables support for Sophgo SoC platform hardware.
+
 config ARCH_STARFIVE
 	def_bool SOC_STARFIVE
 

arch/riscv/boot/dts/Makefile

@@ -4,6 +4,7 @@ subdir-y += canaan
 subdir-y += microchip
 subdir-y += renesas
 subdir-y += sifive
+subdir-y += sophgo
 subdir-y += starfive
 subdir-y += thead