drm/i915: Enable GGTT updates with binder in MTL

nirmoy · nirmoy · commit 799d794f7559 · 2023-09-30T13:49:36.000+02:00
MTL can hang because of a HW bug while parallel reading/writing from/to LMEM/GTTMMADR BAR so try to reduce GGTT update related pci transactions with blitter command as recommended for Wa_13010847436 and Wa_14019519902. Signed-off-by: Nirmoy Das <nirmoy.das@intel.com> Reviewed-by: Oak Zeng <oak.zeng@intel.com> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230926083742.14740-8-nirmoy.das@intel.com
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -23,7 +23,8 @@
 
 bool i915_ggtt_require_binder(struct drm_i915_private *i915)
 {
-	return false;
+	/* Wa_13010847436 & Wa_14019519902 */
+	return MEDIA_VER_FULL(i915) == IP_VER(13, 0);
 }
 
 static bool intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *i915)

Original file line number	Diff line number	Diff line change
`@@ -23,7 +23,8 @@`
`23`	`23`
`24`	`24`	`bool i915_ggtt_require_binder(struct drm_i915_private *i915)`
`25`	`25`	`{`
`26`		`- return false;`
	`26`	`+ /* Wa_13010847436 & Wa_14019519902 */`
	`27`	`+ return MEDIA_VER_FULL(i915) == IP_VER(13, 0);`
`27`	`28`	`}`
`28`	`29`
`29`	`30`	`static bool intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *i915)`