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86 | 86 | xlnx,use-parity = <0>; |
87 | 87 | }; |
88 | 88 |
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89 | | - Some IP cores actually implement 2 or more logical devices. In |
90 | | - this case, the device should still describe the whole IP core with |
91 | | - a single node and add a child node for each logical device. The |
92 | | - ranges property can be used to translate from parent IP-core to the |
93 | | - registers of each device. In addition, the parent node should be |
94 | | - compatible with the bus type 'xlnx,compound', and should contain |
95 | | - #address-cells and #size-cells, as with any other bus. (Note: this |
96 | | - makes the assumption that both logical devices have the same bus |
97 | | - binding. If this is not true, then separate nodes should be used |
98 | | - for each logical device). The 'cell-index' property can be used to |
99 | | - enumerate logical devices within an IP core. For example, the |
100 | | - following is the system.mhs entry for the dual ps2 controller found |
101 | | - on the ml403 reference design. |
102 | | - |
103 | | - BEGIN opb_ps2_dual_ref |
104 | | - PARAMETER INSTANCE = opb_ps2_dual_ref_0 |
105 | | - PARAMETER HW_VER = 1.00.a |
106 | | - PARAMETER C_BASEADDR = 0xA9000000 |
107 | | - PARAMETER C_HIGHADDR = 0xA9001FFF |
108 | | - BUS_INTERFACE SOPB = opb_v20_0 |
109 | | - PORT Sys_Intr1 = ps2_1_intr |
110 | | - PORT Sys_Intr2 = ps2_2_intr |
111 | | - PORT Clkin1 = ps2_clk_rx_1 |
112 | | - PORT Clkin2 = ps2_clk_rx_2 |
113 | | - PORT Clkpd1 = ps2_clk_tx_1 |
114 | | - PORT Clkpd2 = ps2_clk_tx_2 |
115 | | - PORT Rx1 = ps2_d_rx_1 |
116 | | - PORT Rx2 = ps2_d_rx_2 |
117 | | - PORT Txpd1 = ps2_d_tx_1 |
118 | | - PORT Txpd2 = ps2_d_tx_2 |
119 | | - END |
120 | | - |
121 | | - It would result in the following device tree nodes: |
122 | | - |
123 | | - opb_ps2_dual_ref_0: opb-ps2-dual-ref@a9000000 { |
124 | | - #address-cells = <1>; |
125 | | - #size-cells = <1>; |
126 | | - compatible = "xlnx,compound"; |
127 | | - ranges = <0 a9000000 2000>; |
128 | | - // If this device had extra parameters, then they would |
129 | | - // go here. |
130 | | - ps2@0 { |
131 | | - compatible = "xlnx,opb-ps2-dual-ref-1.00.a"; |
132 | | - reg = <0 40>; |
133 | | - interrupt-parent = <&opb_intc_0>; |
134 | | - interrupts = <3 0>; |
135 | | - cell-index = <0>; |
136 | | - }; |
137 | | - ps2@1000 { |
138 | | - compatible = "xlnx,opb-ps2-dual-ref-1.00.a"; |
139 | | - reg = <1000 40>; |
140 | | - interrupt-parent = <&opb_intc_0>; |
141 | | - interrupts = <3 0>; |
142 | | - cell-index = <0>; |
143 | | - }; |
144 | | - }; |
145 | | - |
146 | | - Also, the system.mhs file defines bus attachments from the processor |
147 | | - to the devices. The device tree structure should reflect the bus |
148 | | - attachments. Again an example; this system.mhs fragment: |
149 | | - |
150 | | - BEGIN ppc405_virtex4 |
151 | | - PARAMETER INSTANCE = ppc405_0 |
152 | | - PARAMETER HW_VER = 1.01.a |
153 | | - BUS_INTERFACE DPLB = plb_v34_0 |
154 | | - BUS_INTERFACE IPLB = plb_v34_0 |
155 | | - END |
156 | | - |
157 | | - BEGIN opb_intc |
158 | | - PARAMETER INSTANCE = opb_intc_0 |
159 | | - PARAMETER HW_VER = 1.00.c |
160 | | - PARAMETER C_BASEADDR = 0xD1000FC0 |
161 | | - PARAMETER C_HIGHADDR = 0xD1000FDF |
162 | | - BUS_INTERFACE SOPB = opb_v20_0 |
163 | | - END |
164 | | - |
165 | | - BEGIN opb_uart16550 |
166 | | - PARAMETER INSTANCE = opb_uart16550_0 |
167 | | - PARAMETER HW_VER = 1.00.d |
168 | | - PARAMETER C_BASEADDR = 0xa0000000 |
169 | | - PARAMETER C_HIGHADDR = 0xa0001FFF |
170 | | - BUS_INTERFACE SOPB = opb_v20_0 |
171 | | - END |
172 | | - |
173 | | - BEGIN plb_v34 |
174 | | - PARAMETER INSTANCE = plb_v34_0 |
175 | | - PARAMETER HW_VER = 1.02.a |
176 | | - END |
177 | | - |
178 | | - BEGIN plb_bram_if_cntlr |
179 | | - PARAMETER INSTANCE = plb_bram_if_cntlr_0 |
180 | | - PARAMETER HW_VER = 1.00.b |
181 | | - PARAMETER C_BASEADDR = 0xFFFF0000 |
182 | | - PARAMETER C_HIGHADDR = 0xFFFFFFFF |
183 | | - BUS_INTERFACE SPLB = plb_v34_0 |
184 | | - END |
185 | | - |
186 | | - BEGIN plb2opb_bridge |
187 | | - PARAMETER INSTANCE = plb2opb_bridge_0 |
188 | | - PARAMETER HW_VER = 1.01.a |
189 | | - PARAMETER C_RNG0_BASEADDR = 0x20000000 |
190 | | - PARAMETER C_RNG0_HIGHADDR = 0x3FFFFFFF |
191 | | - PARAMETER C_RNG1_BASEADDR = 0x60000000 |
192 | | - PARAMETER C_RNG1_HIGHADDR = 0x7FFFFFFF |
193 | | - PARAMETER C_RNG2_BASEADDR = 0x80000000 |
194 | | - PARAMETER C_RNG2_HIGHADDR = 0xBFFFFFFF |
195 | | - PARAMETER C_RNG3_BASEADDR = 0xC0000000 |
196 | | - PARAMETER C_RNG3_HIGHADDR = 0xDFFFFFFF |
197 | | - BUS_INTERFACE SPLB = plb_v34_0 |
198 | | - BUS_INTERFACE MOPB = opb_v20_0 |
199 | | - END |
200 | | - |
201 | | - Gives this device tree (some properties removed for clarity): |
202 | | - |
203 | | - plb@0 { |
204 | | - #address-cells = <1>; |
205 | | - #size-cells = <1>; |
206 | | - compatible = "xlnx,plb-v34-1.02.a"; |
207 | | - device_type = "ibm,plb"; |
208 | | - ranges; // 1:1 translation |
209 | | - |
210 | | - plb_bram_if_cntrl_0: bram@ffff0000 { |
211 | | - reg = <ffff0000 10000>; |
212 | | - } |
213 | | - |
214 | | - opb@20000000 { |
215 | | - #address-cells = <1>; |
216 | | - #size-cells = <1>; |
217 | | - ranges = <20000000 20000000 20000000 |
218 | | - 60000000 60000000 20000000 |
219 | | - 80000000 80000000 40000000 |
220 | | - c0000000 c0000000 20000000>; |
221 | | - |
222 | | - opb_uart16550_0: serial@a0000000 { |
223 | | - reg = <a00000000 2000>; |
224 | | - }; |
225 | | - |
226 | | - opb_intc_0: interrupt-controller@d1000fc0 { |
227 | | - reg = <d1000fc0 20>; |
228 | | - }; |
229 | | - }; |
230 | | - }; |
231 | | - |
232 | 89 | That covers the general approach to binding xilinx IP cores into the |
233 | 90 | device tree. The following are bindings for specific devices: |
234 | 91 |
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