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Merge tag 'samsung-clk-6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into clk-samsung
Pull more Samsung clk driver updates from Krzysztof Kozlowski: - ExynosAutov920: add support for additional clock controllers (M2M and MFC) * tag 'samsung-clk-6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: clk: samsung: clk-pll: simplify samsung_pll_lock_wait() clk: samsung: exynosautov920: add block mfc clock support clk: samsung: exynosautov920: add clock support dt-bindings: clock: exynosautov920: add mfc clock definitions dt-bindings: clock: exynosautov920: add m2m clock definitions dt-bindings: clock: google,gs101-clock: add power-domains
2 parents 4424419 + d669ec6 commit 7ee9719

5 files changed

Lines changed: 155 additions & 31 deletions

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‎Documentation/devicetree/bindings/clock/google,gs101-clock.yaml‎

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Original file line numberDiff line numberDiff line change
@@ -46,6 +46,9 @@ properties:
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"#clock-cells":
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const: 1
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power-domains:
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maxItems: 1
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reg:
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maxItems: 1
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‎Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml‎

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Original file line numberDiff line numberDiff line change
@@ -38,6 +38,8 @@ properties:
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- samsung,exynosautov920-cmu-hsi0
3939
- samsung,exynosautov920-cmu-hsi1
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- samsung,exynosautov920-cmu-hsi2
41+
- samsung,exynosautov920-cmu-m2m
42+
- samsung,exynosautov920-cmu-mfc
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- samsung,exynosautov920-cmu-misc
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- samsung,exynosautov920-cmu-peric0
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- samsung,exynosautov920-cmu-peric1
@@ -226,6 +228,46 @@ allOf:
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- const: embd
227229
- const: ethernet
228230

231+
- if:
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properties:
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compatible:
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contains:
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const: samsung,exynosautov920-cmu-m2m
236+
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (38.4 MHz)
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- description: CMU_M2M NOC clock (from CMU_TOP)
243+
- description: CMU_M2M JPEG clock (from CMU_TOP)
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clock-names:
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items:
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- const: oscclk
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- const: noc
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- const: jpeg
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynosautov920-cmu-mfc
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (38.4 MHz)
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- description: CMU_MFC MFC clock (from CMU_TOP)
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- description: CMU_MFC WFD clock (from CMU_TOP)
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clock-names:
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items:
267+
- const: oscclk
268+
- const: mfc
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- const: wfd
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required:
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- compatible
231273
- "#clock-cells"

‎drivers/clk/samsung/clk-exynosautov920.c‎

Lines changed: 90 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -27,6 +27,8 @@
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#define CLKS_NR_HSI0 (CLK_DOUT_HSI0_PCIE_APB + 1)
2828
#define CLKS_NR_HSI1 (CLK_MOUT_HSI1_USBDRD + 1)
2929
#define CLKS_NR_HSI2 (CLK_DOUT_HSI2_ETHERNET_PTP + 1)
30+
#define CLKS_NR_M2M (CLK_DOUT_M2M_NOCP + 1)
31+
#define CLKS_NR_MFC (CLK_DOUT_MFC_NOCP + 1)
3032

3133
/* ---- CMU_TOP ------------------------------------------------------------ */
3234

@@ -1821,6 +1823,88 @@ static const struct samsung_cmu_info hsi2_cmu_info __initconst = {
18211823
.clk_name = "noc",
18221824
};
18231825

1826+
/* ---- CMU_M2M --------------------------------------------------------- */
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1828+
/* Register Offset definitions for CMU_M2M (0x1a800000) */
1829+
#define PLL_CON0_MUX_CLKCMU_M2M_JPEG_USER 0x600
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#define PLL_CON0_MUX_CLKCMU_M2M_NOC_USER 0x610
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#define CLK_CON_DIV_DIV_CLK_M2M_NOCP 0x1800
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1833+
static const unsigned long m2m_clk_regs[] __initconst = {
1834+
PLL_CON0_MUX_CLKCMU_M2M_JPEG_USER,
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PLL_CON0_MUX_CLKCMU_M2M_NOC_USER,
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CLK_CON_DIV_DIV_CLK_M2M_NOCP,
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};
1838+
1839+
/* List of parent clocks for Muxes in CMU_M2M */
1840+
PNAME(mout_clkcmu_m2m_noc_user_p) = { "oscclk", "dout_clkcmu_m2m_noc" };
1841+
PNAME(mout_clkcmu_m2m_jpeg_user_p) = { "oscclk", "dout_clkcmu_m2m_jpeg" };
1842+
1843+
static const struct samsung_mux_clock m2m_mux_clks[] __initconst = {
1844+
MUX(CLK_MOUT_M2M_JPEG_USER, "mout_clkcmu_m2m_jpeg_user",
1845+
mout_clkcmu_m2m_jpeg_user_p, PLL_CON0_MUX_CLKCMU_M2M_JPEG_USER, 4, 1),
1846+
MUX(CLK_MOUT_M2M_NOC_USER, "mout_clkcmu_m2m_noc_user",
1847+
mout_clkcmu_m2m_noc_user_p, PLL_CON0_MUX_CLKCMU_M2M_NOC_USER, 4, 1),
1848+
};
1849+
1850+
static const struct samsung_div_clock m2m_div_clks[] __initconst = {
1851+
DIV(CLK_DOUT_M2M_NOCP, "dout_m2m_nocp",
1852+
"mout_clkcmu_m2m_noc_user", CLK_CON_DIV_DIV_CLK_M2M_NOCP,
1853+
0, 3),
1854+
};
1855+
1856+
static const struct samsung_cmu_info m2m_cmu_info __initconst = {
1857+
.mux_clks = m2m_mux_clks,
1858+
.nr_mux_clks = ARRAY_SIZE(m2m_mux_clks),
1859+
.div_clks = m2m_div_clks,
1860+
.nr_div_clks = ARRAY_SIZE(m2m_div_clks),
1861+
.nr_clk_ids = CLKS_NR_M2M,
1862+
.clk_regs = m2m_clk_regs,
1863+
.nr_clk_regs = ARRAY_SIZE(m2m_clk_regs),
1864+
.clk_name = "noc",
1865+
};
1866+
1867+
/* ---- CMU_MFC --------------------------------------------------------- */
1868+
1869+
/* Register Offset definitions for CMU_MFC (0x19c00000) */
1870+
#define PLL_CON0_MUX_CLKCMU_MFC_MFC_USER 0x600
1871+
#define PLL_CON0_MUX_CLKCMU_MFC_WFD_USER 0x610
1872+
#define CLK_CON_DIV_DIV_CLK_MFC_NOCP 0x1800
1873+
1874+
static const unsigned long mfc_clk_regs[] __initconst = {
1875+
PLL_CON0_MUX_CLKCMU_MFC_MFC_USER,
1876+
PLL_CON0_MUX_CLKCMU_MFC_WFD_USER,
1877+
CLK_CON_DIV_DIV_CLK_MFC_NOCP,
1878+
};
1879+
1880+
/* List of parent clocks for Muxes in CMU_MFC */
1881+
PNAME(mout_clkcmu_mfc_mfc_user_p) = { "oscclk", "dout_clkcmu_mfc_mfc" };
1882+
PNAME(mout_clkcmu_mfc_wfd_user_p) = { "oscclk", "dout_clkcmu_mfc_wfd" };
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1884+
static const struct samsung_mux_clock mfc_mux_clks[] __initconst = {
1885+
MUX(CLK_MOUT_MFC_MFC_USER, "mout_clkcmu_mfc_mfc_user",
1886+
mout_clkcmu_mfc_mfc_user_p, PLL_CON0_MUX_CLKCMU_MFC_MFC_USER, 4, 1),
1887+
MUX(CLK_MOUT_MFC_WFD_USER, "mout_clkcmu_mfc_wfd_user",
1888+
mout_clkcmu_mfc_wfd_user_p, PLL_CON0_MUX_CLKCMU_MFC_WFD_USER, 4, 1),
1889+
};
1890+
1891+
static const struct samsung_div_clock mfc_div_clks[] __initconst = {
1892+
DIV(CLK_DOUT_MFC_NOCP, "dout_mfc_nocp",
1893+
"mout_clkcmu_mfc_mfc_user", CLK_CON_DIV_DIV_CLK_MFC_NOCP,
1894+
0, 3),
1895+
};
1896+
1897+
static const struct samsung_cmu_info mfc_cmu_info __initconst = {
1898+
.mux_clks = mfc_mux_clks,
1899+
.nr_mux_clks = ARRAY_SIZE(mfc_mux_clks),
1900+
.div_clks = mfc_div_clks,
1901+
.nr_div_clks = ARRAY_SIZE(mfc_div_clks),
1902+
.nr_clk_ids = CLKS_NR_MFC,
1903+
.clk_regs = mfc_clk_regs,
1904+
.nr_clk_regs = ARRAY_SIZE(mfc_clk_regs),
1905+
.clk_name = "noc",
1906+
};
1907+
18241908
static int __init exynosautov920_cmu_probe(struct platform_device *pdev)
18251909
{
18261910
const struct samsung_cmu_info *info;
@@ -1851,6 +1935,12 @@ static const struct of_device_id exynosautov920_cmu_of_match[] = {
18511935
}, {
18521936
.compatible = "samsung,exynosautov920-cmu-hsi2",
18531937
.data = &hsi2_cmu_info,
1938+
}, {
1939+
.compatible = "samsung,exynosautov920-cmu-m2m",
1940+
.data = &m2m_cmu_info,
1941+
}, {
1942+
.compatible = "samsung,exynosautov920-cmu-mfc",
1943+
.data = &mfc_cmu_info,
18541944
},
18551945
{ }
18561946
};

‎drivers/clk/samsung/clk-pll.c‎

Lines changed: 10 additions & 31 deletions
Original file line numberDiff line numberDiff line change
@@ -11,14 +11,12 @@
1111
#include <linux/iopoll.h>
1212
#include <linux/delay.h>
1313
#include <linux/slab.h>
14-
#include <linux/timekeeping.h>
1514
#include <linux/clk-provider.h>
1615
#include <linux/io.h>
1716
#include "clk.h"
1817
#include "clk-pll.h"
1918

20-
#define PLL_TIMEOUT_US 20000U
21-
#define PLL_TIMEOUT_LOOPS 1000000U
19+
#define PLL_TIMEOUT_LOOPS 20000U
2220

2321
struct samsung_clk_pll {
2422
struct clk_hw hw;
@@ -71,20 +69,11 @@ static int samsung_pll_determine_rate(struct clk_hw *hw,
7169
return 0;
7270
}
7371

74-
static bool pll_early_timeout = true;
75-
76-
static int __init samsung_pll_disable_early_timeout(void)
77-
{
78-
pll_early_timeout = false;
79-
return 0;
80-
}
81-
arch_initcall(samsung_pll_disable_early_timeout);
82-
8372
/* Wait until the PLL is locked */
8473
static int samsung_pll_lock_wait(struct samsung_clk_pll *pll,
8574
unsigned int reg_mask)
8675
{
87-
int i, ret;
76+
int ret;
8877
u32 val;
8978

9079
/*
@@ -93,25 +82,15 @@ static int samsung_pll_lock_wait(struct samsung_clk_pll *pll,
9382
* initialized, another when the timekeeping is suspended. udelay() also
9483
* cannot be used when the clocksource is not running on arm64, since
9584
* the current timer is used as cycle counter. So a simple busy loop
96-
* is used here in that special cases. The limit of iterations has been
97-
* derived from experimental measurements of various PLLs on multiple
98-
* Exynos SoC variants. Single register read time was usually in range
99-
* 0.4...1.5 us, never less than 0.4 us.
85+
* is used here.
86+
* The limit of iterations has been derived from experimental
87+
* measurements of various PLLs on multiple Exynos SoC variants. Single
88+
* register read time was usually in range 0.4...1.5 us, never less than
89+
* 0.4 us.
10090
*/
101-
if (pll_early_timeout || timekeeping_suspended) {
102-
i = PLL_TIMEOUT_LOOPS;
103-
while (i-- > 0) {
104-
if (readl_relaxed(pll->con_reg) & reg_mask)
105-
return 0;
106-
107-
cpu_relax();
108-
}
109-
ret = -ETIMEDOUT;
110-
} else {
111-
ret = readl_relaxed_poll_timeout_atomic(pll->con_reg, val,
112-
val & reg_mask, 0, PLL_TIMEOUT_US);
113-
}
114-
91+
ret = readl_relaxed_poll_timeout_atomic(pll->con_reg, val,
92+
val & reg_mask, 0,
93+
PLL_TIMEOUT_LOOPS);
11594
if (ret < 0)
11695
pr_err("Could not lock PLL %s\n", clk_hw_get_name(&pll->hw));
11796

‎include/dt-bindings/clock/samsung,exynosautov920.h‎

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Original file line numberDiff line numberDiff line change
@@ -295,4 +295,14 @@
295295
#define CLK_DOUT_HSI2_ETHERNET 6
296296
#define CLK_DOUT_HSI2_ETHERNET_PTP 7
297297

298+
/* CMU_M2M */
299+
#define CLK_MOUT_M2M_JPEG_USER 1
300+
#define CLK_MOUT_M2M_NOC_USER 2
301+
#define CLK_DOUT_M2M_NOCP 3
302+
303+
/* CMU_MFC */
304+
#define CLK_MOUT_MFC_MFC_USER 1
305+
#define CLK_MOUT_MFC_WFD_USER 2
306+
#define CLK_DOUT_MFC_NOCP 3
307+
298308
#endif /* _DT_BINDINGS_CLOCK_EXYNOSAUTOV920_H */

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