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djbwdavejiang
djbw
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cxl/port: Move dport RAS setup to dport add time
Towards the end goal of making all CXL RAS capability handling uniform across host bridge ports, upstream switch ports, and endpoint ports, move dport RAS setup. Move it to cxl_switch_port_probe() context for switch / VH dports (via cxl_port_add_dport()) and cxl_endpoint_port_probe() context for an RCH dport. Rename the RAS setup helper to devm_cxl_dport_ras_setup() for symmetry with devm_cxl_switch_port_decoders_setup(). Only the RCH version needs to be exported and the cxl_test mocking can be deleted with a dev_is_pci() check on the dport_dev. Reviewed-by: Dave Jiang <dave.jiang@intel.com> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Tested-by: Terry Bowman <terry.bowman@amd.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com> Link: https://patch.msgid.link/20260131000403.2135324-7-dan.j.williams@intel.com Signed-off-by: Dave Jiang <dave.jiang@intel.com>
1 parent 3864cb6 commit 7f5ff74

8 files changed

Lines changed: 47 additions & 39 deletions

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‎drivers/cxl/core/core.h‎

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -144,6 +144,14 @@ int cxl_pci_get_bandwidth(struct pci_dev *pdev, struct access_coordinate *c);
144144
int cxl_port_get_switch_dport_bandwidth(struct cxl_port *port,
145145
struct access_coordinate *c);
146146

147+
static inline struct device *dport_to_host(struct cxl_dport *dport)
148+
{
149+
struct cxl_port *port = dport->port;
150+
151+
if (is_cxl_root(port))
152+
return port->uport_dev;
153+
return &port->dev;
154+
}
147155
#ifdef CONFIG_CXL_RAS
148156
int cxl_ras_init(void);
149157
void cxl_ras_exit(void);
@@ -152,6 +160,7 @@ void cxl_handle_cor_ras(struct device *dev, void __iomem *ras_base);
152160
void cxl_dport_map_rch_aer(struct cxl_dport *dport);
153161
void cxl_disable_rch_root_ints(struct cxl_dport *dport);
154162
void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds);
163+
void devm_cxl_dport_ras_setup(struct cxl_dport *dport);
155164
#else
156165
static inline int cxl_ras_init(void)
157166
{
@@ -166,6 +175,7 @@ static inline void cxl_handle_cor_ras(struct device *dev, void __iomem *ras_base
166175
static inline void cxl_dport_map_rch_aer(struct cxl_dport *dport) { }
167176
static inline void cxl_disable_rch_root_ints(struct cxl_dport *dport) { }
168177
static inline void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds) { }
178+
static inline void devm_cxl_dport_ras_setup(struct cxl_dport *dport) { }
169179
#endif /* CONFIG_CXL_RAS */
170180

171181
int cxl_gpf_port_setup(struct cxl_dport *dport);

‎drivers/cxl/core/port.c‎

Lines changed: 3 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1119,15 +1119,6 @@ static void cxl_dport_unlink(void *data)
11191119
sysfs_remove_link(&port->dev.kobj, link_name);
11201120
}
11211121

1122-
static struct device *dport_to_host(struct cxl_dport *dport)
1123-
{
1124-
struct cxl_port *port = dport->port;
1125-
1126-
if (is_cxl_root(port))
1127-
return port->uport_dev;
1128-
return &port->dev;
1129-
}
1130-
11311122
static void free_dport(void *dport)
11321123
{
11331124
kfree(dport);
@@ -1261,6 +1252,9 @@ __devm_cxl_add_dport(struct cxl_port *port, struct device *dport_dev,
12611252

12621253
cxl_debugfs_create_dport_dir(dport);
12631254

1255+
if (!dport->rch)
1256+
devm_cxl_dport_ras_setup(dport);
1257+
12641258
/* keep the group, and mark the end of devm actions */
12651259
cxl_dport_close_dr_group(dport, no_free_ptr(dport_dr_group));
12661260

‎drivers/cxl/core/ras.c‎

Lines changed: 18 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -139,26 +139,32 @@ static void cxl_dport_map_ras(struct cxl_dport *dport)
139139
}
140140

141141
/**
142-
* cxl_dport_init_ras_reporting - Setup CXL RAS report on this dport
142+
* devm_cxl_dport_ras_setup - Setup CXL RAS report on this dport
143143
* @dport: the cxl_dport that needs to be initialized
144-
* @host: host device for devm operations
145144
*/
146-
void cxl_dport_init_ras_reporting(struct cxl_dport *dport, struct device *host)
145+
void devm_cxl_dport_ras_setup(struct cxl_dport *dport)
147146
{
148-
dport->reg_map.host = host;
147+
dport->reg_map.host = dport_to_host(dport);
149148
cxl_dport_map_ras(dport);
149+
}
150150

151-
if (dport->rch) {
152-
struct pci_host_bridge *host_bridge = to_pci_host_bridge(dport->dport_dev);
151+
void devm_cxl_dport_rch_ras_setup(struct cxl_dport *dport)
152+
{
153+
struct pci_host_bridge *host_bridge;
153154

154-
if (!host_bridge->native_aer)
155-
return;
155+
if (!dev_is_pci(dport->dport_dev))
156+
return;
156157

157-
cxl_dport_map_rch_aer(dport);
158-
cxl_disable_rch_root_ints(dport);
159-
}
158+
devm_cxl_dport_ras_setup(dport);
159+
160+
host_bridge = to_pci_host_bridge(dport->dport_dev);
161+
if (!host_bridge->native_aer)
162+
return;
163+
164+
cxl_dport_map_rch_aer(dport);
165+
cxl_disable_rch_root_ints(dport);
160166
}
161-
EXPORT_SYMBOL_NS_GPL(cxl_dport_init_ras_reporting, "CXL");
167+
EXPORT_SYMBOL_NS_GPL(devm_cxl_dport_rch_ras_setup, "CXL");
162168

163169
void cxl_handle_cor_ras(struct device *dev, void __iomem *ras_base)
164170
{

‎drivers/cxl/cxlpci.h‎

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -81,7 +81,7 @@ void read_cdat_data(struct cxl_port *port);
8181
void cxl_cor_error_detected(struct pci_dev *pdev);
8282
pci_ers_result_t cxl_error_detected(struct pci_dev *pdev,
8383
pci_channel_state_t state);
84-
void cxl_dport_init_ras_reporting(struct cxl_dport *dport, struct device *host);
84+
void devm_cxl_dport_rch_ras_setup(struct cxl_dport *dport);
8585
#else
8686
static inline void cxl_cor_error_detected(struct pci_dev *pdev) { }
8787

@@ -91,8 +91,9 @@ static inline pci_ers_result_t cxl_error_detected(struct pci_dev *pdev,
9191
return PCI_ERS_RESULT_NONE;
9292
}
9393

94-
static inline void cxl_dport_init_ras_reporting(struct cxl_dport *dport,
95-
struct device *host) { }
94+
static inline void devm_cxl_dport_rch_ras_setup(struct cxl_dport *dport)
95+
{
96+
}
9697
#endif
9798

9899
#endif /* __CXL_PCI_H__ */

‎drivers/cxl/mem.c‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -166,8 +166,6 @@ static int cxl_mem_probe(struct device *dev)
166166
else
167167
endpoint_parent = &parent_port->dev;
168168

169-
cxl_dport_init_ras_reporting(dport, dev);
170-
171169
scoped_guard(device, endpoint_parent) {
172170
if (!endpoint_parent->driver) {
173171
dev_err(dev, "CXL port topology %s not enabled\n",

‎drivers/cxl/port.c‎

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -71,6 +71,7 @@ static int cxl_switch_port_probe(struct cxl_port *port)
7171
static int cxl_endpoint_port_probe(struct cxl_port *port)
7272
{
7373
struct cxl_memdev *cxlmd = to_cxl_memdev(port->uport_dev);
74+
struct cxl_dport *dport = port->parent_dport;
7475
int rc;
7576

7677
/* Cache the data early to ensure is_visible() works */
@@ -86,6 +87,17 @@ static int cxl_endpoint_port_probe(struct cxl_port *port)
8687
if (rc)
8788
return rc;
8889

90+
/*
91+
* With VH (CXL Virtual Host) topology the cxl_port::add_dport() method
92+
* handles RAS setup for downstream ports. With RCH (CXL Restricted CXL
93+
* Host) topologies the downstream port is enumerated early by platform
94+
* firmware, but the RCRB (root complex register block) is not mapped
95+
* until after the cxl_pci driver attaches to the RCIeP (root complex
96+
* integrated endpoint).
97+
*/
98+
if (dport->rch)
99+
devm_cxl_dport_rch_ras_setup(dport);
100+
89101
/*
90102
* Now that all endpoint decoders are successfully enumerated, try to
91103
* assemble regions from committed decoders

‎tools/testing/cxl/Kbuild‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,6 @@ ldflags-y += --wrap=nvdimm_bus_register
77
ldflags-y += --wrap=cxl_await_media_ready
88
ldflags-y += --wrap=devm_cxl_add_rch_dport
99
ldflags-y += --wrap=cxl_endpoint_parse_cdat
10-
ldflags-y += --wrap=cxl_dport_init_ras_reporting
1110
ldflags-y += --wrap=devm_cxl_endpoint_decoders_setup
1211
ldflags-y += --wrap=hmat_get_extended_linear_cache_size
1312
ldflags-y += --wrap=devm_cxl_add_dport_by_dev

‎tools/testing/cxl/test/mock.c‎

Lines changed: 0 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -234,18 +234,6 @@ void __wrap_cxl_endpoint_parse_cdat(struct cxl_port *port)
234234
}
235235
EXPORT_SYMBOL_NS_GPL(__wrap_cxl_endpoint_parse_cdat, "CXL");
236236

237-
void __wrap_cxl_dport_init_ras_reporting(struct cxl_dport *dport, struct device *host)
238-
{
239-
int index;
240-
struct cxl_mock_ops *ops = get_cxl_mock_ops(&index);
241-
242-
if (!ops || !ops->is_mock_port(dport->dport_dev))
243-
cxl_dport_init_ras_reporting(dport, host);
244-
245-
put_cxl_mock_ops(index);
246-
}
247-
EXPORT_SYMBOL_NS_GPL(__wrap_cxl_dport_init_ras_reporting, "CXL");
248-
249237
struct cxl_dport *__wrap_devm_cxl_add_dport_by_dev(struct cxl_port *port,
250238
struct device *dport_dev)
251239
{

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