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Luo Jieandersson
Luo Jie
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dt-bindings: clock: add qca8386/qca8084 clock and reset definitions
QCA8386/QCA8084 includes the clock & reset controller that is accessed by MDIO bus. Two work modes are supported, qca8386 works as switch mode, qca8084 works as PHY mode. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Luo Jie <quic_luoj@quicinc.com> Link: https://lore.kernel.org/r/20240605124541.2711467-3-quic_luoj@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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‎Documentation/devicetree/bindings/clock/qcom,qca8k-nsscc.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,qca8k-nsscc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm NSS Clock & Reset Controller on QCA8386/QCA8084
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maintainers:
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- Bjorn Andersson <andersson@kernel.org>
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- Luo Jie <quic_luoj@quicinc.com>
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description: |
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Qualcomm NSS clock control module provides the clocks and resets
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on QCA8386(switch mode)/QCA8084(PHY mode)
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See also::
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include/dt-bindings/clock/qcom,qca8k-nsscc.h
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include/dt-bindings/reset/qcom,qca8k-nsscc.h
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properties:
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compatible:
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oneOf:
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- const: qcom,qca8084-nsscc
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- items:
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- enum:
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- qcom,qca8082-nsscc
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- qcom,qca8085-nsscc
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- qcom,qca8384-nsscc
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- qcom,qca8385-nsscc
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- qcom,qca8386-nsscc
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- const: qcom,qca8084-nsscc
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clocks:
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items:
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- description: Chip reference clock source
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- description: UNIPHY0 RX 312P5M/125M clock source
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- description: UNIPHY0 TX 312P5M/125M clock source
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- description: UNIPHY1 RX 312P5M/125M clock source
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- description: UNIPHY1 TX 312P5M/125M clock source
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- description: UNIPHY1 RX 312P5M clock source
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- description: UNIPHY1 TX 312P5M clock source
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reg:
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items:
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- description: MDIO bus address for Clock & Reset Controller register
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reset-gpios:
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description: GPIO connected to the chip
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maxItems: 1
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required:
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- compatible
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- clocks
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- reg
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- reset-gpios
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allOf:
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- $ref: qcom,gcc.yaml#
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/gpio/gpio.h>
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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clock-controller@18 {
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compatible = "qcom,qca8084-nsscc";
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reg = <0x18>;
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reset-gpios = <&tlmm 51 GPIO_ACTIVE_LOW>;
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clocks = <&pcs0_pll>,
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<&qca8k_uniphy0_rx>,
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<&qca8k_uniphy0_tx>,
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<&qca8k_uniphy1_rx>,
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<&qca8k_uniphy1_tx>,
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<&qca8k_uniphy1_rx312p5m>,
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<&qca8k_uniphy1_tx312p5m>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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};
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...

‎include/dt-bindings/clock/qcom,qca8k-nsscc.h‎

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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_QCA8K_NSS_CC_H
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#define _DT_BINDINGS_CLK_QCOM_QCA8K_NSS_CC_H
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#define NSS_CC_SWITCH_CORE_CLK_SRC 0
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#define NSS_CC_SWITCH_CORE_CLK 1
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#define NSS_CC_APB_BRIDGE_CLK 2
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#define NSS_CC_MAC0_TX_CLK_SRC 3
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#define NSS_CC_MAC0_TX_DIV_CLK_SRC 4
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#define NSS_CC_MAC0_TX_CLK 5
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#define NSS_CC_MAC0_TX_SRDS1_CLK 6
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#define NSS_CC_MAC0_RX_CLK_SRC 7
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#define NSS_CC_MAC0_RX_DIV_CLK_SRC 8
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#define NSS_CC_MAC0_RX_CLK 9
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#define NSS_CC_MAC0_RX_SRDS1_CLK 10
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#define NSS_CC_MAC1_TX_CLK_SRC 11
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#define NSS_CC_MAC1_TX_DIV_CLK_SRC 12
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#define NSS_CC_MAC1_SRDS1_CH0_XGMII_RX_DIV_CLK_SRC 13
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#define NSS_CC_MAC1_SRDS1_CH0_RX_CLK 14
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#define NSS_CC_MAC1_TX_CLK 15
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#define NSS_CC_MAC1_GEPHY0_TX_CLK 16
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#define NSS_CC_MAC1_SRDS1_CH0_XGMII_RX_CLK 17
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#define NSS_CC_MAC1_RX_CLK_SRC 18
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#define NSS_CC_MAC1_RX_DIV_CLK_SRC 19
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#define NSS_CC_MAC1_SRDS1_CH0_XGMII_TX_DIV_CLK_SRC 20
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#define NSS_CC_MAC1_SRDS1_CH0_TX_CLK 21
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#define NSS_CC_MAC1_RX_CLK 22
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#define NSS_CC_MAC1_GEPHY0_RX_CLK 23
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#define NSS_CC_MAC1_SRDS1_CH0_XGMII_TX_CLK 24
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#define NSS_CC_MAC2_TX_CLK_SRC 25
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#define NSS_CC_MAC2_TX_DIV_CLK_SRC 26
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#define NSS_CC_MAC2_SRDS1_CH1_XGMII_RX_DIV_CLK_SRC 27
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#define NSS_CC_MAC2_SRDS1_CH1_RX_CLK 28
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#define NSS_CC_MAC2_TX_CLK 29
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#define NSS_CC_MAC2_GEPHY1_TX_CLK 30
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#define NSS_CC_MAC2_SRDS1_CH1_XGMII_RX_CLK 31
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#define NSS_CC_MAC2_RX_CLK_SRC 32
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#define NSS_CC_MAC2_RX_DIV_CLK_SRC 33
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#define NSS_CC_MAC2_SRDS1_CH1_XGMII_TX_DIV_CLK_SRC 34
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#define NSS_CC_MAC2_SRDS1_CH1_TX_CLK 35
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#define NSS_CC_MAC2_RX_CLK 36
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#define NSS_CC_MAC2_GEPHY1_RX_CLK 37
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#define NSS_CC_MAC2_SRDS1_CH1_XGMII_TX_CLK 38
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#define NSS_CC_MAC3_TX_CLK_SRC 39
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#define NSS_CC_MAC3_TX_DIV_CLK_SRC 40
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#define NSS_CC_MAC3_SRDS1_CH2_XGMII_RX_DIV_CLK_SRC 41
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#define NSS_CC_MAC3_SRDS1_CH2_RX_CLK 42
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#define NSS_CC_MAC3_TX_CLK 43
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#define NSS_CC_MAC3_GEPHY2_TX_CLK 44
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#define NSS_CC_MAC3_SRDS1_CH2_XGMII_RX_CLK 45
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#define NSS_CC_MAC3_RX_CLK_SRC 46
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#define NSS_CC_MAC3_RX_DIV_CLK_SRC 47
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#define NSS_CC_MAC3_SRDS1_CH2_XGMII_TX_DIV_CLK_SRC 48
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#define NSS_CC_MAC3_SRDS1_CH2_TX_CLK 49
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#define NSS_CC_MAC3_RX_CLK 50
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#define NSS_CC_MAC3_GEPHY2_RX_CLK 51
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#define NSS_CC_MAC3_SRDS1_CH2_XGMII_TX_CLK 52
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#define NSS_CC_MAC4_TX_CLK_SRC 53
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#define NSS_CC_MAC4_TX_DIV_CLK_SRC 54
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#define NSS_CC_MAC4_SRDS1_CH3_XGMII_RX_DIV_CLK_SRC 55
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#define NSS_CC_MAC4_SRDS1_CH3_RX_CLK 56
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#define NSS_CC_MAC4_TX_CLK 57
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#define NSS_CC_MAC4_GEPHY3_TX_CLK 58
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#define NSS_CC_MAC4_SRDS1_CH3_XGMII_RX_CLK 59
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#define NSS_CC_MAC4_RX_CLK_SRC 60
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#define NSS_CC_MAC4_RX_DIV_CLK_SRC 61
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#define NSS_CC_MAC4_SRDS1_CH3_XGMII_TX_DIV_CLK_SRC 62
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#define NSS_CC_MAC4_SRDS1_CH3_TX_CLK 63
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#define NSS_CC_MAC4_RX_CLK 64
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#define NSS_CC_MAC4_GEPHY3_RX_CLK 65
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#define NSS_CC_MAC4_SRDS1_CH3_XGMII_TX_CLK 66
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#define NSS_CC_MAC5_TX_CLK_SRC 67
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#define NSS_CC_MAC5_TX_DIV_CLK_SRC 68
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#define NSS_CC_MAC5_TX_SRDS0_CLK 69
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#define NSS_CC_MAC5_TX_CLK 70
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#define NSS_CC_MAC5_RX_CLK_SRC 71
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#define NSS_CC_MAC5_RX_DIV_CLK_SRC 72
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#define NSS_CC_MAC5_RX_SRDS0_CLK 73
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#define NSS_CC_MAC5_RX_CLK 74
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#define NSS_CC_MAC5_TX_SRDS0_CLK_SRC 75
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#define NSS_CC_MAC5_RX_SRDS0_CLK_SRC 76
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#define NSS_CC_AHB_CLK_SRC 77
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#define NSS_CC_AHB_CLK 78
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#define NSS_CC_SEC_CTRL_AHB_CLK 79
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#define NSS_CC_TLMM_CLK 80
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#define NSS_CC_TLMM_AHB_CLK 81
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#define NSS_CC_CNOC_AHB_CLK 82
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#define NSS_CC_MDIO_AHB_CLK 83
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#define NSS_CC_MDIO_MASTER_AHB_CLK 84
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#define NSS_CC_SYS_CLK_SRC 85
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#define NSS_CC_SRDS0_SYS_CLK 86
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#define NSS_CC_SRDS1_SYS_CLK 87
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#define NSS_CC_GEPHY0_SYS_CLK 88
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#define NSS_CC_GEPHY1_SYS_CLK 89
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#define NSS_CC_GEPHY2_SYS_CLK 90
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#define NSS_CC_GEPHY3_SYS_CLK 91
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#endif

‎include/dt-bindings/reset/qcom,qca8k-nsscc.h‎

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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_RESET_QCOM_QCA8K_NSS_CC_H
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#define _DT_BINDINGS_RESET_QCOM_QCA8K_NSS_CC_H
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#define NSS_CC_SWITCH_CORE_ARES 1
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#define NSS_CC_APB_BRIDGE_ARES 2
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#define NSS_CC_MAC0_TX_ARES 3
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#define NSS_CC_MAC0_TX_SRDS1_ARES 4
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#define NSS_CC_MAC0_RX_ARES 5
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#define NSS_CC_MAC0_RX_SRDS1_ARES 6
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#define NSS_CC_MAC1_SRDS1_CH0_RX_ARES 7
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#define NSS_CC_MAC1_TX_ARES 8
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#define NSS_CC_MAC1_GEPHY0_TX_ARES 9
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#define NSS_CC_MAC1_SRDS1_CH0_XGMII_RX_ARES 10
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#define NSS_CC_MAC1_SRDS1_CH0_TX_ARES 11
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#define NSS_CC_MAC1_RX_ARES 12
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#define NSS_CC_MAC1_GEPHY0_RX_ARES 13
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#define NSS_CC_MAC1_SRDS1_CH0_XGMII_TX_ARES 14
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#define NSS_CC_MAC2_SRDS1_CH1_RX_ARES 15
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#define NSS_CC_MAC2_TX_ARES 16
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#define NSS_CC_MAC2_GEPHY1_TX_ARES 17
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#define NSS_CC_MAC2_SRDS1_CH1_XGMII_RX_ARES 18
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#define NSS_CC_MAC2_SRDS1_CH1_TX_ARES 19
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#define NSS_CC_MAC2_RX_ARES 20
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#define NSS_CC_MAC2_GEPHY1_RX_ARES 21
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#define NSS_CC_MAC2_SRDS1_CH1_XGMII_TX_ARES 22
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#define NSS_CC_MAC3_SRDS1_CH2_RX_ARES 23
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#define NSS_CC_MAC3_TX_ARES 24
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#define NSS_CC_MAC3_GEPHY2_TX_ARES 25
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#define NSS_CC_MAC3_SRDS1_CH2_XGMII_RX_ARES 26
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#define NSS_CC_MAC3_SRDS1_CH2_TX_ARES 27
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#define NSS_CC_MAC3_RX_ARES 28
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#define NSS_CC_MAC3_GEPHY2_RX_ARES 29
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#define NSS_CC_MAC3_SRDS1_CH2_XGMII_TX_ARES 30
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#define NSS_CC_MAC4_SRDS1_CH3_RX_ARES 31
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#define NSS_CC_MAC4_TX_ARES 32
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#define NSS_CC_MAC4_GEPHY3_TX_ARES 33
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#define NSS_CC_MAC4_SRDS1_CH3_XGMII_RX_ARES 34
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#define NSS_CC_MAC4_SRDS1_CH3_TX_ARES 35
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#define NSS_CC_MAC4_RX_ARES 36
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#define NSS_CC_MAC4_GEPHY3_RX_ARES 37
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#define NSS_CC_MAC4_SRDS1_CH3_XGMII_TX_ARES 38
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#define NSS_CC_MAC5_TX_ARES 39
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#define NSS_CC_MAC5_TX_SRDS0_ARES 40
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#define NSS_CC_MAC5_RX_ARES 41
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#define NSS_CC_MAC5_RX_SRDS0_ARES 42
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#define NSS_CC_AHB_ARES 43
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#define NSS_CC_SEC_CTRL_AHB_ARES 44
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#define NSS_CC_TLMM_ARES 45
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#define NSS_CC_TLMM_AHB_ARES 46
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#define NSS_CC_CNOC_AHB_ARES 47
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#define NSS_CC_MDIO_AHB_ARES 48
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#define NSS_CC_MDIO_MASTER_AHB_ARES 49
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#define NSS_CC_SRDS0_SYS_ARES 50
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#define NSS_CC_SRDS1_SYS_ARES 51
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#define NSS_CC_GEPHY0_SYS_ARES 52
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#define NSS_CC_GEPHY1_SYS_ARES 53
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#define NSS_CC_GEPHY2_SYS_ARES 54
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#define NSS_CC_GEPHY3_SYS_ARES 55
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#define NSS_CC_SEC_CTRL_ARES 56
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#define NSS_CC_SEC_CTRL_SENSE_ARES 57
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#define NSS_CC_SLEEP_ARES 58
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#define NSS_CC_DEBUG_ARES 59
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#define NSS_CC_GEPHY0_ARES 60
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#define NSS_CC_GEPHY1_ARES 61
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#define NSS_CC_GEPHY2_ARES 62
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#define NSS_CC_GEPHY3_ARES 63
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#define NSS_CC_DSP_ARES 64
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#define NSS_CC_GEPHY_FULL_ARES 65
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#define NSS_CC_GLOBAL_ARES 66
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#define NSS_CC_XPCS_ARES 67
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#endif

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