ARM: dts: imx: move nand related property under nand@0

Add child node nand@0 and move NAND related property under it to align
modern nand-controller.yaml.

Fix below CHECK_DTBS warnings:
  arch/arm/boot/dts/nxp/imx/imx6ull-colibri-aster.dtb: nand-controller@1806000 (fsl,imx6q-gpmi-nand): Unevaluated properties are not allowed ('nand-ecc-mode', 'nand-ecc-step-size', 'nand-ecc-strength', 'nand-on-flash-bbt' were unexpected)
        from schema $id: http://devicetree.org/schemas/mtd/gpmi-nand.yaml#

Since 2019 year, commit
(212e496 dt-bindings: mtd: Add YAML schemas for the generic NAND options)
NAND related property is preferred located under nand@<n> even though only
one NAND chip supported.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

Author: nxpfrankli

arch/arm/boot/dts/nxp/imx/imx6-logicpd-som.dtsi

@@ -36,8 +36,12 @@
 &gpmi {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_gpmi_nand>;
-	nand-on-flash-bbt;
 	status = "okay";
+
+	nand@0 {
+		reg = <0>;
+		nand-on-flash-bbt;
+	};
 };
 
 &i2c3 {

arch/arm/boot/dts/nxp/imx/imx6qdl-icore.dtsi

@@ -172,8 +172,12 @@
 &gpmi {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_gpmi_nand>;
-	nand-on-flash-bbt;
 	status = "okay";
+
+	nand@0 {
+		reg = <0>;
+		nand-on-flash-bbt;
+	};
 };
 
 &i2c1 {

arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-pfla02.dtsi

@@ -102,8 +102,12 @@
 &gpmi {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_gpmi_nand>;
-	nand-on-flash-bbt;
 	status = "okay";
+
+	nand@0 {
+		reg = <0>;
+		nand-on-flash-bbt;
+	};
 };
 
 &i2c1 {

arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi

@@ -73,8 +73,12 @@
 &gpmi {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_gpmi_nand>;
-	nand-on-flash-bbt;
 	status = "disabled";
+
+	nand@0 {
+		reg = <0>;
+		nand-on-flash-bbt;
+	};
 };
 
 &i2c3 {

arch/arm/boot/dts/nxp/imx/imx6qdl-skov-cpu.dtsi

@@ -260,10 +260,14 @@
 &gpmi {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_gpmi_nand>;
-	nand-on-flash-bbt;
 	#address-cells = <1>;
 	#size-cells = <0>;
 	status = "okay";
+
+	nand@0 {
+		reg = <0>;
+		nand-on-flash-bbt;
+	};
 };
 
 &i2c3 {

arch/arm/boot/dts/nxp/imx/imx6qdl-tx6.dtsi

@@ -252,9 +252,13 @@
 &gpmi {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_gpmi_nand>;
-	nand-on-flash-bbt;
 	fsl,no-blockmark-swap;
 	status = "okay";
+
+	nand@0 {
+		reg = <0>;
+		nand-on-flash-bbt;
+	};
 };
 
 &i2c1 {

arch/arm/boot/dts/nxp/imx/imx6ul-geam.dts

@@ -133,8 +133,12 @@
 &gpmi {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_gpmi_nand>;
-	nand-on-flash-bbt;
 	status = "okay";
+
+	nand@0 {
+		reg = <0>;
+		nand-on-flash-bbt;
+	};
 };
 
 &i2c1 {

arch/arm/boot/dts/nxp/imx/imx6ul-isiot.dtsi

@@ -101,8 +101,12 @@
 &gpmi {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_gpmi_nand>;
-	nand-on-flash-bbt;
 	status = "disabled";
+
+	nand@0 {
+		reg = <0>;
+		nand-on-flash-bbt;
+	};
 };
 
 &i2c1 {

arch/arm/boot/dts/nxp/imx/imx6ul-phytec-phycore-som.dtsi

@@ -63,8 +63,12 @@
 &gpmi {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_gpmi_nand>;
-	nand-on-flash-bbt;
 	status = "disabled";
+
+	nand@0 {
+		reg = <0>;
+		nand-on-flash-bbt;
+	};
 };
 
 &i2c1 {

arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul.dtsi

@@ -296,9 +296,13 @@
 &gpmi {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_gpmi_nand>;
-	nand-on-flash-bbt;
 	fsl,no-blockmark-swap;
 	status = "okay";
+
+	nand@0 {
+		reg = <0>;
+		nand-on-flash-bbt;
+	};
 };
 
 &i2c2 {