@@ -416,6 +416,12 @@ static void etnaviv_hw_identify(struct etnaviv_gpu *gpu)
416416 if (gpu -> identity .model == chipModel_GC700 )
417417 gpu -> identity .features &= ~chipFeatures_FAST_CLEAR ;
418418
419+ /* These models/revisions don't have the 2D pipe bit */
420+ if ((gpu -> identity .model == chipModel_GC500 &&
421+ gpu -> identity .revision <= 2 ) ||
422+ gpu -> identity .model == chipModel_GC300 )
423+ gpu -> identity .features |= chipFeatures_PIPE_2D ;
424+
419425 if ((gpu -> identity .model == chipModel_GC500 &&
420426 gpu -> identity .revision < 2 ) ||
421427 (gpu -> identity .model == chipModel_GC300 &&
@@ -449,8 +455,9 @@ static void etnaviv_hw_identify(struct etnaviv_gpu *gpu)
449455 gpu_read (gpu , VIVS_HI_CHIP_MINOR_FEATURE_5 );
450456 }
451457
452- /* GC600 idle register reports zero bits where modules aren't present */
453- if (gpu -> identity .model == chipModel_GC600 )
458+ /* GC600/300 idle register reports zero bits where modules aren't present */
459+ if (gpu -> identity .model == chipModel_GC600 ||
460+ gpu -> identity .model == chipModel_GC300 )
454461 gpu -> idle_mask = VIVS_HI_IDLE_STATE_TX |
455462 VIVS_HI_IDLE_STATE_RA |
456463 VIVS_HI_IDLE_STATE_SE |
@@ -583,17 +590,17 @@ static void etnaviv_gpu_enable_mlcg(struct etnaviv_gpu *gpu)
583590 u32 pmc , ppc ;
584591
585592 /* enable clock gating */
586- ppc = gpu_read (gpu , VIVS_PM_POWER_CONTROLS );
593+ ppc = gpu_read_power (gpu , VIVS_PM_POWER_CONTROLS );
587594 ppc |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING ;
588595
589596 /* Disable stall module clock gating for 4.3.0.1 and 4.3.0.2 revs */
590597 if (gpu -> identity .revision == 0x4301 ||
591598 gpu -> identity .revision == 0x4302 )
592599 ppc |= VIVS_PM_POWER_CONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING ;
593600
594- gpu_write (gpu , VIVS_PM_POWER_CONTROLS , ppc );
601+ gpu_write_power (gpu , VIVS_PM_POWER_CONTROLS , ppc );
595602
596- pmc = gpu_read (gpu , VIVS_PM_MODULE_CONTROLS );
603+ pmc = gpu_read_power (gpu , VIVS_PM_MODULE_CONTROLS );
597604
598605 /* Disable PA clock gating for GC400+ without bugfix except for GC420 */
599606 if (gpu -> identity .model >= chipModel_GC400 &&
@@ -616,19 +623,20 @@ static void etnaviv_gpu_enable_mlcg(struct etnaviv_gpu *gpu)
616623
617624 /* Disable TX clock gating on affected core revisions. */
618625 if (etnaviv_is_model_rev (gpu , GC4000 , 0x5222 ) ||
619- etnaviv_is_model_rev (gpu , GC2000 , 0x5108 ))
626+ etnaviv_is_model_rev (gpu , GC2000 , 0x5108 ) ||
627+ etnaviv_is_model_rev (gpu , GC2000 , 0x6202 ) ||
628+ etnaviv_is_model_rev (gpu , GC2000 , 0x6203 ))
620629 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX ;
621630
622- /* Disable SE, RA and TX clock gating on affected core revisions. */
631+ /* Disable SE and RA clock gating on affected core revisions. */
623632 if (etnaviv_is_model_rev (gpu , GC7000 , 0x6202 ))
624633 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_SE |
625- VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA |
626- VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX ;
634+ VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA ;
627635
628636 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ ;
629637 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ ;
630638
631- gpu_write (gpu , VIVS_PM_MODULE_CONTROLS , pmc );
639+ gpu_write_power (gpu , VIVS_PM_MODULE_CONTROLS , pmc );
632640}
633641
634642void etnaviv_gpu_start_fe (struct etnaviv_gpu * gpu , u32 address , u16 prefetch )
@@ -688,11 +696,11 @@ static void etnaviv_gpu_setup_pulse_eater(struct etnaviv_gpu *gpu)
688696 (gpu -> identity .features & chipFeatures_PIPE_3D ))
689697 {
690698 /* Performance fix: disable internal DFS */
691- pulse_eater = gpu_read (gpu , VIVS_PM_PULSE_EATER );
699+ pulse_eater = gpu_read_power (gpu , VIVS_PM_PULSE_EATER );
692700 pulse_eater |= BIT (18 );
693701 }
694702
695- gpu_write (gpu , VIVS_PM_PULSE_EATER , pulse_eater );
703+ gpu_write_power (gpu , VIVS_PM_PULSE_EATER , pulse_eater );
696704}
697705
698706static void etnaviv_gpu_hw_init (struct etnaviv_gpu * gpu )
@@ -1045,12 +1053,28 @@ int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m)
10451053}
10461054#endif
10471055
1048- void etnaviv_gpu_recover_hang (struct etnaviv_gpu * gpu )
1056+ void etnaviv_gpu_recover_hang (struct etnaviv_gem_submit * submit )
10491057{
1058+ struct etnaviv_gpu * gpu = submit -> gpu ;
1059+ char * comm = NULL , * cmd = NULL ;
1060+ struct task_struct * task ;
10501061 unsigned int i ;
10511062
10521063 dev_err (gpu -> dev , "recover hung GPU!\n" );
10531064
1065+ task = get_pid_task (submit -> pid , PIDTYPE_PID );
1066+ if (task ) {
1067+ comm = kstrdup (task -> comm , GFP_KERNEL );
1068+ cmd = kstrdup_quotable_cmdline (task , GFP_KERNEL );
1069+ put_task_struct (task );
1070+ }
1071+
1072+ if (comm && cmd )
1073+ dev_err (gpu -> dev , "offending task: %s (%s)\n" , comm , cmd );
1074+
1075+ kfree (cmd );
1076+ kfree (comm );
1077+
10541078 if (pm_runtime_get_sync (gpu -> dev ) < 0 )
10551079 goto pm_put ;
10561080
@@ -1294,9 +1318,9 @@ static void sync_point_perfmon_sample_pre(struct etnaviv_gpu *gpu,
12941318 u32 val ;
12951319
12961320 /* disable clock gating */
1297- val = gpu_read (gpu , VIVS_PM_POWER_CONTROLS );
1321+ val = gpu_read_power (gpu , VIVS_PM_POWER_CONTROLS );
12981322 val &= ~VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING ;
1299- gpu_write (gpu , VIVS_PM_POWER_CONTROLS , val );
1323+ gpu_write_power (gpu , VIVS_PM_POWER_CONTROLS , val );
13001324
13011325 /* enable debug register */
13021326 val = gpu_read (gpu , VIVS_HI_CLOCK_CONTROL );
@@ -1327,9 +1351,9 @@ static void sync_point_perfmon_sample_post(struct etnaviv_gpu *gpu,
13271351 gpu_write (gpu , VIVS_HI_CLOCK_CONTROL , val );
13281352
13291353 /* enable clock gating */
1330- val = gpu_read (gpu , VIVS_PM_POWER_CONTROLS );
1354+ val = gpu_read_power (gpu , VIVS_PM_POWER_CONTROLS );
13311355 val |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING ;
1332- gpu_write (gpu , VIVS_PM_POWER_CONTROLS , val );
1356+ gpu_write_power (gpu , VIVS_PM_POWER_CONTROLS , val );
13331357}
13341358
13351359
0 commit comments