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Merge tag 'renesas-drivers-for-v5.19-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/drivers
Renesas driver updates for v5.19 (take two) - Initial support for the R-Car V4H and RZ/V2M SoCs, - Miscellaneous fixes and improvements. * tag 'renesas-drivers-for-v5.19-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: soc: renesas: R-Car V3U is R-Car Gen4 soc: renesas: rzn1: Select PM and PM_GENERIC_DOMAINS configs soc: renesas: Add RZ/V2M (R9A09G011) config option soc: renesas: rcar-rst: Add support for R-Car V4H soc: renesas: Identify R-Car V4H soc: renesas: r8a779g0-sysc: Add r8a779g0 support dt-bindings: clock: Add r8a779g0 CPG Core Clock Definitions dt-bindings: power: Add r8a779g0 SYSC power domain definitions Link: https://lore.kernel.org/r/cover.1651828613.git.geert+renesas@glider.be Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2 parents 15b5b76 + 27e7657 commit 819ed6f

9 files changed

Lines changed: 232 additions & 1 deletion

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‎drivers/soc/renesas/Kconfig‎

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@@ -47,6 +47,8 @@ config ARCH_RZG2L
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config ARCH_RZN1
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bool
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select PM
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select PM_GENERIC_DOMAINS
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select ARM_AMBA
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if ARM && ARCH_RENESAS
@@ -268,6 +270,13 @@ config ARCH_R8A779A0
268270
help
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This enables support for the Renesas R-Car V3U SoC.
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273+
config ARCH_R8A779G0
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bool "ARM64 Platform support for R-Car V4H"
275+
select ARCH_RCAR_GEN3
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select SYSC_R8A779G0
277+
help
278+
This enables support for the Renesas R-Car V4H SoC.
279+
271280
config ARCH_R8A774C0
272281
bool "ARM64 Platform support for RZ/G2E"
273282
select ARCH_RCAR_GEN3
@@ -314,6 +323,13 @@ config ARCH_R9A07G054
314323
help
315324
This enables support for the Renesas RZ/V2L SoC variants.
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326+
config ARCH_R9A09G011
327+
bool "ARM64 Platform support for RZ/V2M"
328+
select PM
329+
select PM_GENERIC_DOMAINS
330+
help
331+
This enables support for the Renesas RZ/V2M SoC.
332+
317333
endif # ARM64
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319335
config RST_RCAR
@@ -385,6 +401,10 @@ config SYSC_R8A779A0
385401
bool "System Controller support for R-Car V3U" if COMPILE_TEST
386402
select SYSC_RCAR_GEN4
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404+
config SYSC_R8A779G0
405+
bool "System Controller support for R-Car V4H" if COMPILE_TEST
406+
select SYSC_RCAR_GEN4
407+
388408
config SYSC_RMOBILE
389409
bool "System Controller support for R-Mobile" if COMPILE_TEST
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‎drivers/soc/renesas/Makefile‎

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@@ -26,6 +26,7 @@ obj-$(CONFIG_SYSC_R8A77990) += r8a77990-sysc.o
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obj-$(CONFIG_SYSC_R8A77995) += r8a77995-sysc.o
2727
obj-$(CONFIG_SYSC_R8A779A0) += r8a779a0-sysc.o
2828
obj-$(CONFIG_SYSC_R8A779F0) += r8a779f0-sysc.o
29+
obj-$(CONFIG_SYSC_R8A779G0) += r8a779g0-sysc.o
2930
ifdef CONFIG_SMP
3031
obj-$(CONFIG_ARCH_R9A06G032) += r9a06g032-smp.o
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endif

‎drivers/soc/renesas/r8a779g0-sysc.c‎

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@@ -0,0 +1,62 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Renesas R-Car V4H System Controller
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*
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* Copyright (C) 2022 Renesas Electronics Corp.
6+
*/
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#include <linux/bits.h>
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#include <linux/clk/renesas.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/of_address.h>
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#include <linux/pm_domain.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/types.h>
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#include <dt-bindings/power/r8a779g0-sysc.h>
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#include "rcar-gen4-sysc.h"
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static struct rcar_gen4_sysc_area r8a779g0_areas[] __initdata = {
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{ "always-on", R8A779G0_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
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{ "a3e0", R8A779G0_PD_A3E0, R8A779G0_PD_ALWAYS_ON, PD_SCU },
29+
{ "a2e0d0", R8A779G0_PD_A2E0D0, R8A779G0_PD_A3E0, PD_SCU },
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{ "a2e0d1", R8A779G0_PD_A2E0D1, R8A779G0_PD_A3E0, PD_SCU },
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{ "a1e0d0c0", R8A779G0_PD_A1E0D0C0, R8A779G0_PD_A2E0D0, PD_CPU_NOCR },
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{ "a1e0d0c1", R8A779G0_PD_A1E0D0C1, R8A779G0_PD_A2E0D0, PD_CPU_NOCR },
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{ "a1e0d1c0", R8A779G0_PD_A1E0D1C0, R8A779G0_PD_A2E0D1, PD_CPU_NOCR },
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{ "a1e0d1c1", R8A779G0_PD_A1E0D1C1, R8A779G0_PD_A2E0D1, PD_CPU_NOCR },
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{ "a33dga", R8A779G0_PD_A33DGA, R8A779G0_PD_ALWAYS_ON },
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{ "a23dgb", R8A779G0_PD_A23DGB, R8A779G0_PD_A33DGA },
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{ "a3vip0", R8A779G0_PD_A3VIP0, R8A779G0_PD_ALWAYS_ON },
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{ "a3vip1", R8A779G0_PD_A3VIP1, R8A779G0_PD_ALWAYS_ON },
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{ "a3vip2", R8A779G0_PD_A3VIP2, R8A779G0_PD_ALWAYS_ON },
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{ "a3isp0", R8A779G0_PD_A3ISP0, R8A779G0_PD_ALWAYS_ON },
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{ "a3isp1", R8A779G0_PD_A3ISP1, R8A779G0_PD_ALWAYS_ON },
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{ "a3ir", R8A779G0_PD_A3IR, R8A779G0_PD_ALWAYS_ON },
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{ "a2cn0", R8A779G0_PD_A2CN0, R8A779G0_PD_A3IR },
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{ "a1cnn0", R8A779G0_PD_A1CNN0, R8A779G0_PD_A2CN0 },
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{ "a1dsp0", R8A779G0_PD_A1DSP0, R8A779G0_PD_A2CN0 },
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{ "a1dsp1", R8A779G0_PD_A1DSP1, R8A779G0_PD_A2CN0 },
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{ "a1dsp2", R8A779G0_PD_A1DSP2, R8A779G0_PD_A2CN0 },
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{ "a1dsp3", R8A779G0_PD_A1DSP3, R8A779G0_PD_A2CN0 },
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{ "a2imp01", R8A779G0_PD_A2IMP01, R8A779G0_PD_A3IR },
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{ "a2imp23", R8A779G0_PD_A2IMP23, R8A779G0_PD_A3IR },
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{ "a2psc", R8A779G0_PD_A2PSC, R8A779G0_PD_A3IR },
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{ "a2dma", R8A779G0_PD_A2DMA, R8A779G0_PD_A3IR },
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{ "a2cv0", R8A779G0_PD_A2CV0, R8A779G0_PD_A3IR },
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{ "a2cv1", R8A779G0_PD_A2CV1, R8A779G0_PD_A3IR },
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{ "a2cv2", R8A779G0_PD_A2CV2, R8A779G0_PD_A3IR },
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{ "a2cv3", R8A779G0_PD_A2CV3, R8A779G0_PD_A3IR },
57+
};
58+
59+
const struct rcar_gen4_sysc_info r8a779g0_sysc_info __initconst = {
60+
.areas = r8a779g0_areas,
61+
.num_areas = ARRAY_SIZE(r8a779g0_areas),
62+
};

‎drivers/soc/renesas/rcar-gen4-sysc.c‎

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@@ -281,6 +281,9 @@ static const struct of_device_id rcar_gen4_sysc_matches[] __initconst = {
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#endif
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#ifdef CONFIG_SYSC_R8A779F0
283283
{ .compatible = "renesas,r8a779f0-sysc", .data = &r8a779f0_sysc_info },
284+
#endif
285+
#ifdef CONFIG_SYSC_R8A779G0
286+
{ .compatible = "renesas,r8a779g0-sysc", .data = &r8a779g0_sysc_info },
284287
#endif
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{ /* sentinel */ }
286289
};

‎drivers/soc/renesas/rcar-gen4-sysc.h‎

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@@ -39,5 +39,6 @@ struct rcar_gen4_sysc_info {
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extern const struct rcar_gen4_sysc_info r8a779a0_sysc_info;
4141
extern const struct rcar_gen4_sysc_info r8a779f0_sysc_info;
42+
extern const struct rcar_gen4_sysc_info r8a779g0_sysc_info;
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4344
#endif /* __SOC_RENESAS_RCAR_GEN4_SYSC_H__ */

‎drivers/soc/renesas/rcar-rst.c‎

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@@ -103,6 +103,7 @@ static const struct of_device_id rcar_rst_matches[] __initconst = {
103103
/* R-Car Gen4 */
104104
{ .compatible = "renesas,r8a779a0-rst", .data = &rcar_rst_gen4 },
105105
{ .compatible = "renesas,r8a779f0-rst", .data = &rcar_rst_gen4 },
106+
{ .compatible = "renesas,r8a779g0-rst", .data = &rcar_rst_gen4 },
106107
{ /* sentinel */ }
107108
};
108109

‎drivers/soc/renesas/renesas-soc.c‎

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@@ -232,7 +232,7 @@ static const struct renesas_soc soc_rcar_d3 __initconst __maybe_unused = {
232232
};
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234234
static const struct renesas_soc soc_rcar_v3u __initconst __maybe_unused = {
235-
.family = &fam_rcar_gen3,
235+
.family = &fam_rcar_gen4,
236236
.id = 0x59,
237237
};
238238

@@ -241,6 +241,11 @@ static const struct renesas_soc soc_rcar_s4 __initconst __maybe_unused = {
241241
.id = 0x5a,
242242
};
243243

244+
static const struct renesas_soc soc_rcar_v4h __initconst __maybe_unused = {
245+
.family = &fam_rcar_gen4,
246+
.id = 0x5c,
247+
};
248+
244249
static const struct renesas_soc soc_shmobile_ag5 __initconst __maybe_unused = {
245250
.family = &fam_shmobile,
246251
.id = 0x37,
@@ -349,6 +354,9 @@ static const struct of_device_id renesas_socs[] __initconst = {
349354
#ifdef CONFIG_ARCH_R8A779F0
350355
{ .compatible = "renesas,r8a779f0", .data = &soc_rcar_s4 },
351356
#endif
357+
#ifdef CONFIG_ARCH_R8A779G0
358+
{ .compatible = "renesas,r8a779g0", .data = &soc_rcar_v4h },
359+
#endif
352360
#if defined(CONFIG_ARCH_R9A07G043)
353361
{ .compatible = "renesas,r9a07g043", .data = &soc_rz_g2ul },
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#endif

‎include/dt-bindings/clock/r8a779g0-cpg-mssr.h‎

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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (C) 2022 Renesas Electronics Corp.
4+
*/
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#ifndef __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__
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#define __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__
7+
8+
#include <dt-bindings/clock/renesas-cpg-mssr.h>
9+
10+
/* r8a779g0 CPG Core Clocks */
11+
12+
#define R8A779G0_CLK_ZX 0
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#define R8A779G0_CLK_ZS 1
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#define R8A779G0_CLK_ZT 2
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#define R8A779G0_CLK_ZTR 3
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#define R8A779G0_CLK_S0D2 4
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#define R8A779G0_CLK_S0D3 5
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#define R8A779G0_CLK_S0D4 6
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#define R8A779G0_CLK_S0D1_VIO 7
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#define R8A779G0_CLK_S0D2_VIO 8
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#define R8A779G0_CLK_S0D4_VIO 9
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#define R8A779G0_CLK_S0D8_VIO 10
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#define R8A779G0_CLK_S0D1_VC 11
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#define R8A779G0_CLK_S0D2_VC 12
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#define R8A779G0_CLK_S0D4_VC 13
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#define R8A779G0_CLK_S0D2_MM 14
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#define R8A779G0_CLK_S0D4_MM 15
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#define R8A779G0_CLK_S0D2_U3DG 16
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#define R8A779G0_CLK_S0D4_U3DG 17
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#define R8A779G0_CLK_S0D2_RT 18
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#define R8A779G0_CLK_S0D3_RT 19
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#define R8A779G0_CLK_S0D4_RT 20
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#define R8A779G0_CLK_S0D6_RT 21
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#define R8A779G0_CLK_S0D24_RT 22
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#define R8A779G0_CLK_S0D2_PER 23
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#define R8A779G0_CLK_S0D3_PER 24
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#define R8A779G0_CLK_S0D4_PER 25
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#define R8A779G0_CLK_S0D6_PER 26
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#define R8A779G0_CLK_S0D12_PER 27
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#define R8A779G0_CLK_S0D24_PER 28
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#define R8A779G0_CLK_S0D1_HSC 29
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#define R8A779G0_CLK_S0D2_HSC 30
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#define R8A779G0_CLK_S0D4_HSC 31
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#define R8A779G0_CLK_S0D2_CC 32
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#define R8A779G0_CLK_SVD1_IR 33
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#define R8A779G0_CLK_SVD2_IR 34
47+
#define R8A779G0_CLK_SVD1_VIP 35
48+
#define R8A779G0_CLK_SVD2_VIP 36
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#define R8A779G0_CLK_CL 37
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#define R8A779G0_CLK_CL16M 38
51+
#define R8A779G0_CLK_CL16M_MM 39
52+
#define R8A779G0_CLK_CL16M_RT 40
53+
#define R8A779G0_CLK_CL16M_PER 41
54+
#define R8A779G0_CLK_CL16M_HSC 42
55+
#define R8A779G0_CLK_Z0 43
56+
#define R8A779G0_CLK_ZB3 44
57+
#define R8A779G0_CLK_ZB3D2 45
58+
#define R8A779G0_CLK_ZB3D4 46
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#define R8A779G0_CLK_ZG 47
60+
#define R8A779G0_CLK_SD0H 48
61+
#define R8A779G0_CLK_SD0 49
62+
#define R8A779G0_CLK_RPC 50
63+
#define R8A779G0_CLK_RPCD2 51
64+
#define R8A779G0_CLK_MSO 52
65+
#define R8A779G0_CLK_CANFD 53
66+
#define R8A779G0_CLK_CSI 54
67+
#define R8A779G0_CLK_FRAY 55
68+
#define R8A779G0_CLK_IPC 56
69+
#define R8A779G0_CLK_SASYNCRT 57
70+
#define R8A779G0_CLK_SASYNCPERD1 58
71+
#define R8A779G0_CLK_SASYNCPERD2 59
72+
#define R8A779G0_CLK_SASYNCPERD4 60
73+
#define R8A779G0_CLK_VIOBUS 61
74+
#define R8A779G0_CLK_VIOBUSD2 62
75+
#define R8A779G0_CLK_VCBUS 63
76+
#define R8A779G0_CLK_VCBUSD2 64
77+
#define R8A779G0_CLK_DSIEXT 65
78+
#define R8A779G0_CLK_DSIREF 66
79+
#define R8A779G0_CLK_ADGH 67
80+
#define R8A779G0_CLK_OSC 68
81+
#define R8A779G0_CLK_ZR0 69
82+
#define R8A779G0_CLK_ZR1 70
83+
#define R8A779G0_CLK_ZR2 71
84+
#define R8A779G0_CLK_IMPA 72
85+
#define R8A779G0_CLK_IMPAD4 73
86+
#define R8A779G0_CLK_CPEX 74
87+
#define R8A779G0_CLK_CBFUSA 75
88+
#define R8A779G0_CLK_R 76
89+
90+
#endif /* __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__ */

‎include/dt-bindings/power/r8a779g0-sysc.h‎

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1+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2+
/*
3+
* Copyright (C) 2022 Renesas Electronics Corp.
4+
*/
5+
#ifndef __DT_BINDINGS_POWER_R8A779G0_SYSC_H__
6+
#define __DT_BINDINGS_POWER_R8A779G0_SYSC_H__
7+
8+
/*
9+
* These power domain indices match the Power Domain Register Numbers (PDR)
10+
*/
11+
12+
#define R8A779G0_PD_A1E0D0C0 0
13+
#define R8A779G0_PD_A1E0D0C1 1
14+
#define R8A779G0_PD_A1E0D1C0 2
15+
#define R8A779G0_PD_A1E0D1C1 3
16+
#define R8A779G0_PD_A2E0D0 16
17+
#define R8A779G0_PD_A2E0D1 17
18+
#define R8A779G0_PD_A3E0 20
19+
#define R8A779G0_PD_A33DGA 24
20+
#define R8A779G0_PD_A23DGB 25
21+
#define R8A779G0_PD_A1DSP0 33
22+
#define R8A779G0_PD_A2IMP01 34
23+
#define R8A779G0_PD_A2PSC 35
24+
#define R8A779G0_PD_A2CV0 36
25+
#define R8A779G0_PD_A2CV1 37
26+
#define R8A779G0_PD_A1CNN0 41
27+
#define R8A779G0_PD_A2CN0 42
28+
#define R8A779G0_PD_A3IR 43
29+
#define R8A779G0_PD_A1DSP1 45
30+
#define R8A779G0_PD_A2IMP23 46
31+
#define R8A779G0_PD_A2DMA 47
32+
#define R8A779G0_PD_A2CV2 48
33+
#define R8A779G0_PD_A2CV3 49
34+
#define R8A779G0_PD_A1DSP2 53
35+
#define R8A779G0_PD_A1DSP3 54
36+
#define R8A779G0_PD_A3VIP0 56
37+
#define R8A779G0_PD_A3VIP1 57
38+
#define R8A779G0_PD_A3VIP2 58
39+
#define R8A779G0_PD_A3ISP0 60
40+
#define R8A779G0_PD_A3ISP1 61
41+
42+
/* Always-on power area */
43+
#define R8A779G0_PD_ALWAYS_ON 64
44+
45+
#endif /* __DT_BINDINGS_POWER_R8A779G0_SYSC_H__*/

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