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bjorn-helgaasbjorn-helgaas
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Merge branch 'pci/host/mt7621'
- Add MediaTek MT7621 SoC PCIe host controller (moved from staging) (Sergio Paracuellos) * pci/host/mt7621: MAINTAINERS: Add Sergio Paracuellos as MT7621 PCIe maintainer PCI: mt7621: Add MediaTek MT7621 PCIe host controller driver dt-bindings: PCI: Add MT7621 SoC PCIe host controller # Conflicts: # drivers/pci/controller/Kconfig # drivers/pci/controller/Makefile
2 parents 581e8fc + 370ea5a commit 83e168d

12 files changed

Lines changed: 172 additions & 134 deletions

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‎Documentation/devicetree/bindings/pci/mediatek,mt7621-pcie.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/mediatek,mt7621-pcie.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MediaTek MT7621 PCIe controller
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maintainers:
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- Sergio Paracuellos <sergio.paracuellos@gmail.com>
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description: |+
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MediaTek MT7621 PCIe subsys supports a single Root Complex (RC)
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with 3 Root Ports. Each Root Port supports a Gen1 1-lane Link
15+
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allOf:
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- $ref: /schemas/pci/pci-bus.yaml#
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properties:
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compatible:
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const: mediatek,mt7621-pci
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23+
reg:
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items:
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- description: host-pci bridge registers
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- description: pcie port 0 RC control registers
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- description: pcie port 1 RC control registers
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- description: pcie port 2 RC control registers
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ranges:
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maxItems: 2
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33+
patternProperties:
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'pcie@[0-2],0':
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type: object
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$ref: /schemas/pci/pci-bus.yaml#
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properties:
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resets:
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maxItems: 1
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clocks:
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maxItems: 1
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phys:
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maxItems: 1
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required:
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- "#interrupt-cells"
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- interrupt-map-mask
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- interrupt-map
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- resets
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- clocks
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- phys
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- phy-names
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- ranges
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unevaluatedProperties: false
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required:
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- compatible
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- reg
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- ranges
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- "#interrupt-cells"
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- interrupt-map-mask
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- interrupt-map
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- reset-gpios
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/mips-gic.h>
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pcie: pcie@1e140000 {
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compatible = "mediatek,mt7621-pci";
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reg = <0x1e140000 0x100>,
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<0x1e142000 0x100>,
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<0x1e143000 0x100>,
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<0x1e144000 0x100>;
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83+
#address-cells = <3>;
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#size-cells = <2>;
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pinctrl-names = "default";
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pinctrl-0 = <&pcie_pins>;
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device_type = "pci";
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ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>, /* pci memory */
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<0x01000000 0 0x1e160000 0x1e160000 0 0x00010000>; /* io space */
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#interrupt-cells = <1>;
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interrupt-map-mask = <0xF800 0 0 0>;
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interrupt-map = <0x0000 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>,
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<0x0800 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
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<0x1000 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
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reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
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pcie@0,0 {
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reg = <0x0000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&rstctrl 24>;
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clocks = <&clkctrl 24>;
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phys = <&pcie0_phy 1>;
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phy-names = "pcie-phy0";
109+
ranges;
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};
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pcie@1,0 {
113+
reg = <0x0800 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&rstctrl 25>;
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clocks = <&clkctrl 25>;
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phys = <&pcie0_phy 1>;
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phy-names = "pcie-phy1";
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ranges;
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};
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pcie@2,0 {
128+
reg = <0x1000 0 0 0 0>;
129+
#address-cells = <3>;
130+
#size-cells = <2>;
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device_type = "pci";
132+
#interrupt-cells = <1>;
133+
interrupt-map-mask = <0 0 0 0>;
134+
interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
135+
resets = <&rstctrl 26>;
136+
clocks = <&clkctrl 26>;
137+
phys = <&pcie2_phy 0>;
138+
phy-names = "pcie-phy2";
139+
ranges;
140+
};
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};
142+
...

‎MAINTAINERS‎

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@@ -11849,6 +11849,12 @@ S: Maintained
1184911849
F: Documentation/devicetree/bindings/i2c/i2c-mt7621.txt
1185011850
F: drivers/i2c/busses/i2c-mt7621.c
1185111851

11852+
MEDIATEK MT7621 PCIE CONTROLLER DRIVER
11853+
M: Sergio Paracuellos <sergio.paracuellos@gmail.com>
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S: Maintained
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F: Documentation/devicetree/bindings/pci/mediatek,mt7621-pcie.yaml
11856+
F: drivers/pci/controller/pcie-mt7621.c
11857+
1185211858
MEDIATEK MT7621 PHY PCI DRIVER
1185311859
M: Sergio Paracuellos <sergio.paracuellos@gmail.com>
1185411860
S: Maintained

‎arch/mips/ralink/Kconfig‎

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Original file line numberDiff line numberDiff line change
@@ -51,7 +51,8 @@ choice
5151
select SYS_SUPPORTS_HIGHMEM
5252
select MIPS_GIC
5353
select CLKSRC_MIPS_GIC
54-
select HAVE_PCI if PCI_MT7621
54+
select HAVE_PCI
55+
select PCI_DRIVERS_GENERIC
5556
select SOC_BUS
5657
endchoice
5758

‎drivers/pci/controller/Kconfig‎

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@@ -330,6 +330,14 @@ config PCIE_APPLE
330330

331331
If unsure, say Y if you have an Apple Silicon system.
332332

333+
config PCIE_MT7621
334+
tristate "MediaTek MT7621 PCIe Controller"
335+
depends on (RALINK && SOC_MT7621) || (MIPS && COMPILE_TEST)
336+
select PHY_MT7621_PCI
337+
default SOC_MT7621
338+
help
339+
This selects a driver for the MediaTek MT7621 PCIe Controller.
340+
333341
source "drivers/pci/controller/dwc/Kconfig"
334342
source "drivers/pci/controller/mobiveil/Kconfig"
335343
source "drivers/pci/controller/cadence/Kconfig"

‎drivers/pci/controller/Makefile‎

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@@ -38,6 +38,8 @@ obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o
3838
obj-$(CONFIG_PCI_LOONGSON) += pci-loongson.o
3939
obj-$(CONFIG_PCIE_HISI_ERR) += pcie-hisi-error.o
4040
obj-$(CONFIG_PCIE_APPLE) += pcie-apple.o
41+
obj-$(CONFIG_PCIE_MT7621) += pcie-mt7621.o
42+
4143
# pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW
4244
obj-y += dwc/
4345
obj-y += mobiveil/

drivers/staging/mt7621-pci/pci-mt7621.c renamed to drivers/pci/controller/pcie-mt7621.c

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@@ -30,18 +30,18 @@
3030
#include <linux/reset.h>
3131
#include <linux/sys_soc.h>
3232

33-
/* MediaTek specific configuration registers */
33+
/* MediaTek-specific configuration registers */
3434
#define PCIE_FTS_NUM 0x70c
3535
#define PCIE_FTS_NUM_MASK GENMASK(15, 8)
3636
#define PCIE_FTS_NUM_L0(x) (((x) & 0xff) << 8)
3737

3838
/* Host-PCI bridge registers */
3939
#define RALINK_PCI_PCICFG_ADDR 0x0000
40-
#define RALINK_PCI_PCIMSK_ADDR 0x000C
40+
#define RALINK_PCI_PCIMSK_ADDR 0x000c
4141
#define RALINK_PCI_CONFIG_ADDR 0x0020
4242
#define RALINK_PCI_CONFIG_DATA 0x0024
4343
#define RALINK_PCI_MEMBASE 0x0028
44-
#define RALINK_PCI_IOBASE 0x002C
44+
#define RALINK_PCI_IOBASE 0x002c
4545

4646
/* PCIe RC control registers */
4747
#define RALINK_PCI_ID 0x0030
@@ -132,7 +132,7 @@ static inline void pcie_port_write(struct mt7621_pcie_port *port,
132132
static inline u32 mt7621_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
133133
unsigned int func, unsigned int where)
134134
{
135-
return (((where & 0xF00) >> 8) << 24) | (bus << 16) | (slot << 11) |
135+
return (((where & 0xf00) >> 8) << 24) | (bus << 16) | (slot << 11) |
136136
(func << 8) | (where & 0xfc) | 0x80000000;
137137
}
138138

@@ -217,7 +217,7 @@ static int setup_cm_memory_region(struct pci_host_bridge *host)
217217

218218
entry = resource_list_first_type(&host->windows, IORESOURCE_MEM);
219219
if (!entry) {
220-
dev_err(dev, "Cannot get memory resource\n");
220+
dev_err(dev, "cannot get memory resource\n");
221221
return -EINVAL;
222222
}
223223

@@ -280,7 +280,7 @@ static int mt7621_pcie_parse_port(struct mt7621_pcie *pcie,
280280
port->gpio_rst = devm_gpiod_get_index_optional(dev, "reset", slot,
281281
GPIOD_OUT_LOW);
282282
if (IS_ERR(port->gpio_rst)) {
283-
dev_err(dev, "Failed to get GPIO for PCIe%d\n", slot);
283+
dev_err(dev, "failed to get GPIO for PCIe%d\n", slot);
284284
err = PTR_ERR(port->gpio_rst);
285285
goto remove_reset;
286286
}
@@ -409,7 +409,7 @@ static int mt7621_pcie_init_ports(struct mt7621_pcie *pcie)
409409

410410
err = mt7621_pcie_init_port(port);
411411
if (err) {
412-
dev_err(dev, "Initiating port %d failed\n", slot);
412+
dev_err(dev, "initializing port %d failed\n", slot);
413413
list_del(&port->list);
414414
}
415415
}
@@ -476,7 +476,7 @@ static int mt7621_pcie_enable_ports(struct pci_host_bridge *host)
476476

477477
entry = resource_list_first_type(&host->windows, IORESOURCE_IO);
478478
if (!entry) {
479-
dev_err(dev, "Cannot get io resource\n");
479+
dev_err(dev, "cannot get io resource\n");
480480
return -EINVAL;
481481
}
482482

@@ -541,25 +541,25 @@ static int mt7621_pci_probe(struct platform_device *pdev)
541541

542542
err = mt7621_pcie_parse_dt(pcie);
543543
if (err) {
544-
dev_err(dev, "Parsing DT failed\n");
544+
dev_err(dev, "parsing DT failed\n");
545545
return err;
546546
}
547547

548548
err = mt7621_pcie_init_ports(pcie);
549549
if (err) {
550-
dev_err(dev, "Nothing connected in virtual bridges\n");
550+
dev_err(dev, "nothing connected in virtual bridges\n");
551551
return 0;
552552
}
553553

554554
err = mt7621_pcie_enable_ports(bridge);
555555
if (err) {
556-
dev_err(dev, "Error enabling pcie ports\n");
556+
dev_err(dev, "error enabling pcie ports\n");
557557
goto remove_resets;
558558
}
559559

560560
err = setup_cm_memory_region(bridge);
561561
if (err) {
562-
dev_err(dev, "Error setting up iocu mem regions\n");
562+
dev_err(dev, "error setting up iocu mem regions\n");
563563
goto remove_resets;
564564
}
565565

‎drivers/staging/Kconfig‎

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@@ -86,8 +86,6 @@ source "drivers/staging/vc04_services/Kconfig"
8686

8787
source "drivers/staging/pi433/Kconfig"
8888

89-
source "drivers/staging/mt7621-pci/Kconfig"
90-
9189
source "drivers/staging/mt7621-dma/Kconfig"
9290

9391
source "drivers/staging/ralink-gdma/Kconfig"

‎drivers/staging/Makefile‎

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@@ -33,7 +33,6 @@ obj-$(CONFIG_KS7010) += ks7010/
3333
obj-$(CONFIG_GREYBUS) += greybus/
3434
obj-$(CONFIG_BCM2835_VCHIQ) += vc04_services/
3535
obj-$(CONFIG_PI433) += pi433/
36-
obj-$(CONFIG_PCI_MT7621) += mt7621-pci/
3736
obj-$(CONFIG_SOC_MT7621) += mt7621-dma/
3837
obj-$(CONFIG_DMA_RALINK) += ralink-gdma/
3938
obj-$(CONFIG_SOC_MT7621) += mt7621-dts/

‎drivers/staging/mt7621-pci/Kconfig‎

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This file was deleted.

‎drivers/staging/mt7621-pci/Makefile‎

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This file was deleted.

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