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MrVanShawn Guo
MrVan
authored and
Shawn Guo
committed
arm64: dts: imx8mp-venice-gw74xx: correct pad settings
According to RM bit layout, BIT3 and BIT0 are reserved. 8 7 6 5 4 3 2 1 0 PE HYS PUE ODE FSEL X DSE X Should not set reserved bit. Fixes: 7899eb6 ("arm64: dts: imx: Add i.MX8M Plus Gateworks gw7400 dts support") Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
1 parent 0836de5 commit 843af59

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Lines changed: 58 additions & 58 deletions

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‎arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts‎

Lines changed: 58 additions & 58 deletions
Original file line numberDiff line numberDiff line change
@@ -622,15 +622,15 @@
622622

623623
pinctrl_hog: hoggrp {
624624
fsl,pins = <
625-
MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x40000041 /* DIO0 */
626-
MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x40000041 /* DIO1 */
627-
MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x40000041 /* M2SKT_OFF# */
628-
MX8MP_IOMUXC_SD2_DATA2__GPIO2_IO17 0x40000159 /* PCIE1_WDIS# */
629-
MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18 0x40000159 /* PCIE2_WDIS# */
630-
MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14 0x40000159 /* PCIE3_WDIS# */
631-
MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x40000041 /* M2SKT_RST# */
632-
MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x40000159 /* M2SKT_WDIS# */
633-
MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x40000159 /* M2SKT_GDIS# */
625+
MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x40000040 /* DIO0 */
626+
MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x40000040 /* DIO1 */
627+
MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x40000040 /* M2SKT_OFF# */
628+
MX8MP_IOMUXC_SD2_DATA2__GPIO2_IO17 0x40000150 /* PCIE1_WDIS# */
629+
MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18 0x40000150 /* PCIE2_WDIS# */
630+
MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14 0x40000150 /* PCIE3_WDIS# */
631+
MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x40000040 /* M2SKT_RST# */
632+
MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x40000150 /* M2SKT_WDIS# */
633+
MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x40000150 /* M2SKT_GDIS# */
634634
MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x40000104 /* UART_TERM */
635635
MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31 0x40000104 /* UART_RS485 */
636636
MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x40000104 /* UART_HALF */
@@ -639,47 +639,47 @@
639639

640640
pinctrl_accel: accelgrp {
641641
fsl,pins = <
642-
MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x159
642+
MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x150
643643
>;
644644
};
645645

646646
pinctrl_eqos: eqosgrp {
647647
fsl,pins = <
648-
MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
649-
MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3
650-
MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
651-
MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
652-
MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91
653-
MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
654-
MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91
655-
MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
656-
MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
657-
MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
658-
MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f
659-
MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f
660-
MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
661-
MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f
662-
MX8MP_IOMUXC_SAI3_RXD__GPIO4_IO30 0x141 /* RST# */
663-
MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x159 /* IRQ# */
648+
MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
649+
MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
650+
MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
651+
MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
652+
MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
653+
MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
654+
MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
655+
MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
656+
MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
657+
MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
658+
MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
659+
MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
660+
MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
661+
MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
662+
MX8MP_IOMUXC_SAI3_RXD__GPIO4_IO30 0x140 /* RST# */
663+
MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x150 /* IRQ# */
664664
>;
665665
};
666666

667667
pinctrl_fec: fecgrp {
668668
fsl,pins = <
669-
MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91
670-
MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91
671-
MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91
672-
MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91
673-
MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91
674-
MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91
675-
MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f
676-
MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f
677-
MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f
678-
MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f
679-
MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f
680-
MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f
681-
MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x141
682-
MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x141
669+
MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90
670+
MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90
671+
MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90
672+
MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90
673+
MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90
674+
MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90
675+
MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16
676+
MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16
677+
MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16
678+
MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16
679+
MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16
680+
MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16
681+
MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x140
682+
MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x140
683683
>;
684684
};
685685

@@ -692,61 +692,61 @@
692692

693693
pinctrl_gsc: gscgrp {
694694
fsl,pins = <
695-
MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x159
695+
MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x150
696696
>;
697697
};
698698

699699
pinctrl_i2c1: i2c1grp {
700700
fsl,pins = <
701-
MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3
702-
MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3
701+
MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2
702+
MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2
703703
>;
704704
};
705705

706706
pinctrl_i2c2: i2c2grp {
707707
fsl,pins = <
708-
MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3
709-
MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3
708+
MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
709+
MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
710710
>;
711711
};
712712

713713
pinctrl_i2c3: i2c3grp {
714714
fsl,pins = <
715-
MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3
716-
MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3
715+
MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
716+
MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2
717717
>;
718718
};
719719

720720
pinctrl_i2c4: i2c4grp {
721721
fsl,pins = <
722-
MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3
723-
MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3
722+
MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c2
723+
MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c2
724724
>;
725725
};
726726

727727
pinctrl_ksz: kszgrp {
728728
fsl,pins = <
729-
MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x159 /* IRQ# */
730-
MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x141 /* RST# */
729+
MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x150 /* IRQ# */
730+
MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x140 /* RST# */
731731
>;
732732
};
733733

734734
pinctrl_gpio_leds: ledgrp {
735735
fsl,pins = <
736-
MX8MP_IOMUXC_SD2_DATA0__GPIO2_IO15 0x19
737-
MX8MP_IOMUXC_SD2_DATA1__GPIO2_IO16 0x19
736+
MX8MP_IOMUXC_SD2_DATA0__GPIO2_IO15 0x10
737+
MX8MP_IOMUXC_SD2_DATA1__GPIO2_IO16 0x10
738738
>;
739739
};
740740

741741
pinctrl_pmic: pmicgrp {
742742
fsl,pins = <
743-
MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x141
743+
MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x140
744744
>;
745745
};
746746

747747
pinctrl_pps: ppsgrp {
748748
fsl,pins = <
749-
MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x141
749+
MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x140
750750
>;
751751
};
752752

@@ -758,13 +758,13 @@
758758

759759
pinctrl_reg_usb2: regusb2grp {
760760
fsl,pins = <
761-
MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x141
761+
MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x140
762762
>;
763763
};
764764

765765
pinctrl_reg_wifi: regwifigrp {
766766
fsl,pins = <
767-
MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x119
767+
MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x110
768768
>;
769769
};
770770

@@ -811,7 +811,7 @@
811811

812812
pinctrl_uart3_gpio: uart3gpiogrp {
813813
fsl,pins = <
814-
MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 0x119
814+
MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 0x110
815815
>;
816816
};
817817

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