@@ -926,19 +926,19 @@ static struct rockchip_mux_route_data rk3568_mux_route_data[] = {
926926 RK_MUXROUTE_PMU (0 , RK_PB5 , 4 , 0x0110 , WRITE_MASK_VAL (3 , 2 , 1 )), /* PWM1 IO mux M1 */
927927 RK_MUXROUTE_PMU (0 , RK_PC1 , 1 , 0x0110 , WRITE_MASK_VAL (5 , 4 , 0 )), /* PWM2 IO mux M0 */
928928 RK_MUXROUTE_PMU (0 , RK_PB6 , 4 , 0x0110 , WRITE_MASK_VAL (5 , 4 , 1 )), /* PWM2 IO mux M1 */
929- RK_MUXROUTE_PMU (0 , RK_PB3 , 2 , 0x0300 , WRITE_MASK_VAL (0 , 0 , 0 )), /* CAN0 IO mux M0 */
929+ RK_MUXROUTE_GRF (0 , RK_PB3 , 2 , 0x0300 , WRITE_MASK_VAL (0 , 0 , 0 )), /* CAN0 IO mux M0 */
930930 RK_MUXROUTE_GRF (2 , RK_PA1 , 4 , 0x0300 , WRITE_MASK_VAL (0 , 0 , 1 )), /* CAN0 IO mux M1 */
931931 RK_MUXROUTE_GRF (1 , RK_PA1 , 3 , 0x0300 , WRITE_MASK_VAL (2 , 2 , 0 )), /* CAN1 IO mux M0 */
932932 RK_MUXROUTE_GRF (4 , RK_PC3 , 3 , 0x0300 , WRITE_MASK_VAL (2 , 2 , 1 )), /* CAN1 IO mux M1 */
933933 RK_MUXROUTE_GRF (4 , RK_PB5 , 3 , 0x0300 , WRITE_MASK_VAL (4 , 4 , 0 )), /* CAN2 IO mux M0 */
934934 RK_MUXROUTE_GRF (2 , RK_PB2 , 4 , 0x0300 , WRITE_MASK_VAL (4 , 4 , 1 )), /* CAN2 IO mux M1 */
935935 RK_MUXROUTE_GRF (4 , RK_PC4 , 1 , 0x0300 , WRITE_MASK_VAL (6 , 6 , 0 )), /* HPDIN IO mux M0 */
936- RK_MUXROUTE_PMU (0 , RK_PC2 , 2 , 0x0300 , WRITE_MASK_VAL (6 , 6 , 1 )), /* HPDIN IO mux M1 */
936+ RK_MUXROUTE_GRF (0 , RK_PC2 , 2 , 0x0300 , WRITE_MASK_VAL (6 , 6 , 1 )), /* HPDIN IO mux M1 */
937937 RK_MUXROUTE_GRF (3 , RK_PB1 , 3 , 0x0300 , WRITE_MASK_VAL (8 , 8 , 0 )), /* GMAC1 IO mux M0 */
938938 RK_MUXROUTE_GRF (4 , RK_PA7 , 3 , 0x0300 , WRITE_MASK_VAL (8 , 8 , 1 )), /* GMAC1 IO mux M1 */
939939 RK_MUXROUTE_GRF (4 , RK_PD1 , 1 , 0x0300 , WRITE_MASK_VAL (10 , 10 , 0 )), /* HDMITX IO mux M0 */
940- RK_MUXROUTE_PMU (0 , RK_PC7 , 1 , 0x0300 , WRITE_MASK_VAL (10 , 10 , 1 )), /* HDMITX IO mux M1 */
941- RK_MUXROUTE_PMU (0 , RK_PB6 , 1 , 0x0300 , WRITE_MASK_VAL (14 , 14 , 0 )), /* I2C2 IO mux M0 */
940+ RK_MUXROUTE_GRF (0 , RK_PC7 , 1 , 0x0300 , WRITE_MASK_VAL (10 , 10 , 1 )), /* HDMITX IO mux M1 */
941+ RK_MUXROUTE_GRF (0 , RK_PB6 , 1 , 0x0300 , WRITE_MASK_VAL (14 , 14 , 0 )), /* I2C2 IO mux M0 */
942942 RK_MUXROUTE_GRF (4 , RK_PB4 , 1 , 0x0300 , WRITE_MASK_VAL (14 , 14 , 1 )), /* I2C2 IO mux M1 */
943943 RK_MUXROUTE_GRF (1 , RK_PA0 , 1 , 0x0304 , WRITE_MASK_VAL (0 , 0 , 0 )), /* I2C3 IO mux M0 */
944944 RK_MUXROUTE_GRF (3 , RK_PB6 , 4 , 0x0304 , WRITE_MASK_VAL (0 , 0 , 1 )), /* I2C3 IO mux M1 */
@@ -964,7 +964,7 @@ static struct rockchip_mux_route_data rk3568_mux_route_data[] = {
964964 RK_MUXROUTE_GRF (4 , RK_PC3 , 1 , 0x0308 , WRITE_MASK_VAL (12 , 12 , 1 )), /* PWM15 IO mux M1 */
965965 RK_MUXROUTE_GRF (3 , RK_PD2 , 3 , 0x0308 , WRITE_MASK_VAL (14 , 14 , 0 )), /* SDMMC2 IO mux M0 */
966966 RK_MUXROUTE_GRF (3 , RK_PA5 , 5 , 0x0308 , WRITE_MASK_VAL (14 , 14 , 1 )), /* SDMMC2 IO mux M1 */
967- RK_MUXROUTE_PMU (0 , RK_PB5 , 2 , 0x030c , WRITE_MASK_VAL (0 , 0 , 0 )), /* SPI0 IO mux M0 */
967+ RK_MUXROUTE_GRF (0 , RK_PB5 , 2 , 0x030c , WRITE_MASK_VAL (0 , 0 , 0 )), /* SPI0 IO mux M0 */
968968 RK_MUXROUTE_GRF (2 , RK_PD3 , 3 , 0x030c , WRITE_MASK_VAL (0 , 0 , 1 )), /* SPI0 IO mux M1 */
969969 RK_MUXROUTE_GRF (2 , RK_PB5 , 3 , 0x030c , WRITE_MASK_VAL (2 , 2 , 0 )), /* SPI1 IO mux M0 */
970970 RK_MUXROUTE_GRF (3 , RK_PC3 , 3 , 0x030c , WRITE_MASK_VAL (2 , 2 , 1 )), /* SPI1 IO mux M1 */
@@ -973,8 +973,8 @@ static struct rockchip_mux_route_data rk3568_mux_route_data[] = {
973973 RK_MUXROUTE_GRF (4 , RK_PB3 , 4 , 0x030c , WRITE_MASK_VAL (6 , 6 , 0 )), /* SPI3 IO mux M0 */
974974 RK_MUXROUTE_GRF (4 , RK_PC2 , 2 , 0x030c , WRITE_MASK_VAL (6 , 6 , 1 )), /* SPI3 IO mux M1 */
975975 RK_MUXROUTE_GRF (2 , RK_PB4 , 2 , 0x030c , WRITE_MASK_VAL (8 , 8 , 0 )), /* UART1 IO mux M0 */
976- RK_MUXROUTE_PMU ( 0 , RK_PD1 , 1 , 0x030c , WRITE_MASK_VAL (8 , 8 , 1 )), /* UART1 IO mux M1 */
977- RK_MUXROUTE_PMU (0 , RK_PD1 , 1 , 0x030c , WRITE_MASK_VAL (10 , 10 , 0 )), /* UART2 IO mux M0 */
976+ RK_MUXROUTE_GRF ( 3 , RK_PD6 , 4 , 0x030c , WRITE_MASK_VAL (8 , 8 , 1 )), /* UART1 IO mux M1 */
977+ RK_MUXROUTE_GRF (0 , RK_PD1 , 1 , 0x030c , WRITE_MASK_VAL (10 , 10 , 0 )), /* UART2 IO mux M0 */
978978 RK_MUXROUTE_GRF (1 , RK_PD5 , 2 , 0x030c , WRITE_MASK_VAL (10 , 10 , 1 )), /* UART2 IO mux M1 */
979979 RK_MUXROUTE_GRF (1 , RK_PA1 , 2 , 0x030c , WRITE_MASK_VAL (12 , 12 , 0 )), /* UART3 IO mux M0 */
980980 RK_MUXROUTE_GRF (3 , RK_PB7 , 4 , 0x030c , WRITE_MASK_VAL (12 , 12 , 1 )), /* UART3 IO mux M1 */
@@ -1004,13 +1004,13 @@ static struct rockchip_mux_route_data rk3568_mux_route_data[] = {
10041004 RK_MUXROUTE_GRF (3 , RK_PD6 , 5 , 0x0314 , WRITE_MASK_VAL (1 , 0 , 1 )), /* PDM IO mux M1 */
10051005 RK_MUXROUTE_GRF (4 , RK_PA0 , 4 , 0x0314 , WRITE_MASK_VAL (1 , 0 , 1 )), /* PDM IO mux M1 */
10061006 RK_MUXROUTE_GRF (3 , RK_PC4 , 5 , 0x0314 , WRITE_MASK_VAL (1 , 0 , 2 )), /* PDM IO mux M2 */
1007- RK_MUXROUTE_PMU (0 , RK_PA5 , 3 , 0x0314 , WRITE_MASK_VAL (3 , 2 , 0 )), /* PCIE20 IO mux M0 */
1007+ RK_MUXROUTE_GRF (0 , RK_PA5 , 3 , 0x0314 , WRITE_MASK_VAL (3 , 2 , 0 )), /* PCIE20 IO mux M0 */
10081008 RK_MUXROUTE_GRF (2 , RK_PD0 , 4 , 0x0314 , WRITE_MASK_VAL (3 , 2 , 1 )), /* PCIE20 IO mux M1 */
10091009 RK_MUXROUTE_GRF (1 , RK_PB0 , 4 , 0x0314 , WRITE_MASK_VAL (3 , 2 , 2 )), /* PCIE20 IO mux M2 */
1010- RK_MUXROUTE_PMU (0 , RK_PA4 , 3 , 0x0314 , WRITE_MASK_VAL (5 , 4 , 0 )), /* PCIE30X1 IO mux M0 */
1010+ RK_MUXROUTE_GRF (0 , RK_PA4 , 3 , 0x0314 , WRITE_MASK_VAL (5 , 4 , 0 )), /* PCIE30X1 IO mux M0 */
10111011 RK_MUXROUTE_GRF (2 , RK_PD2 , 4 , 0x0314 , WRITE_MASK_VAL (5 , 4 , 1 )), /* PCIE30X1 IO mux M1 */
10121012 RK_MUXROUTE_GRF (1 , RK_PA5 , 4 , 0x0314 , WRITE_MASK_VAL (5 , 4 , 2 )), /* PCIE30X1 IO mux M2 */
1013- RK_MUXROUTE_PMU (0 , RK_PA6 , 2 , 0x0314 , WRITE_MASK_VAL (7 , 6 , 0 )), /* PCIE30X2 IO mux M0 */
1013+ RK_MUXROUTE_GRF (0 , RK_PA6 , 2 , 0x0314 , WRITE_MASK_VAL (7 , 6 , 0 )), /* PCIE30X2 IO mux M0 */
10141014 RK_MUXROUTE_GRF (2 , RK_PD4 , 4 , 0x0314 , WRITE_MASK_VAL (7 , 6 , 1 )), /* PCIE30X2 IO mux M1 */
10151015 RK_MUXROUTE_GRF (4 , RK_PC2 , 4 , 0x0314 , WRITE_MASK_VAL (7 , 6 , 2 )), /* PCIE30X2 IO mux M2 */
10161016};
@@ -2436,10 +2436,19 @@ static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
24362436 case RK3308 :
24372437 case RK3368 :
24382438 case RK3399 :
2439+ case RK3568 :
24392440 case RK3588 :
24402441 pull_type = bank -> pull_type [pin_num / 8 ];
24412442 data >>= bit ;
24422443 data &= (1 << RK3188_PULL_BITS_PER_PIN ) - 1 ;
2444+ /*
2445+ * In the TRM, pull-up being 1 for everything except the GPIO0_D3-D6,
2446+ * where that pull up value becomes 3.
2447+ */
2448+ if (ctrl -> type == RK3568 && bank -> bank_num == 0 && pin_num >= 27 && pin_num <= 30 ) {
2449+ if (data == 3 )
2450+ data = 1 ;
2451+ }
24432452
24442453 return rockchip_pull_list [pull_type ][data ];
24452454 default :
@@ -2497,7 +2506,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
24972506 }
24982507 }
24992508 /*
2500- * In the TRM, pull-up being 1 for everything except the GPIO0_D0 -D6,
2509+ * In the TRM, pull-up being 1 for everything except the GPIO0_D3 -D6,
25012510 * where that pull up value becomes 3.
25022511 */
25032512 if (ctrl -> type == RK3568 && bank -> bank_num == 0 && pin_num >= 27 && pin_num <= 30 ) {
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