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Merge tag 'platform-drivers-x86-v5.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pdx86/platform-drivers-x86
Pull x86 platform driver updates from Hans de Goede: "This includes some small changes to kernel/stop_machine.c and arch/x86 which are deps of the new Intel IFS support. Highlights: - New drivers: - Intel "In Field Scan" (IFS) support - Winmate FM07/FM07P buttons - Mellanox SN2201 support - AMD PMC driver enhancements - Lots of various other small fixes and hardware-id additions" * tag 'platform-drivers-x86-v5.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pdx86/platform-drivers-x86: (54 commits) platform/x86/intel/ifs: Add CPU_SUP_INTEL dependency platform/x86: intel_cht_int33fe: Set driver data platform/x86: intel-hid: fix _DSM function index handling platform/x86: toshiba_acpi: use kobj_to_dev() platform/x86: samsung-laptop: use kobj_to_dev() platform/x86: gigabyte-wmi: Add support for Z490 AORUS ELITE AC and X570 AORUS ELITE WIFI tools/power/x86/intel-speed-select: Fix warning for perf_cap.cpu tools/power/x86/intel-speed-select: Display error on turbo mode disabled Documentation: In-Field Scan platform/x86/intel/ifs: add ABI documentation for IFS trace: platform/x86/intel/ifs: Add trace point to track Intel IFS operations platform/x86/intel/ifs: Add IFS sysfs interface platform/x86/intel/ifs: Add scan test support platform/x86/intel/ifs: Authenticate and copy to secured memory platform/x86/intel/ifs: Check IFS Image sanity platform/x86/intel/ifs: Read IFS firmware image platform/x86/intel/ifs: Add stub driver for In-Field Scan stop_machine: Add stop_core_cpuslocked() for per-core operations x86/msr-index: Define INTEGRITY_CAPABILITIES MSR x86/microcode/intel: Expose collect_cpu_info_early() for IFS ...
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Lines changed: 3013 additions & 213 deletions

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‎Documentation/ABI/stable/sysfs-driver-mlxreg-io‎

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@@ -467,3 +467,39 @@ Description: These files provide the maximum powered required for line card
467467
feeding and line card configuration Id.
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469469
The files are read only.
470+
471+
What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/phy_reset
472+
Date: May 2022
473+
KernelVersion: 5.19
474+
Contact: Vadim Pasternak <vadimpmellanox.com>
475+
Description: This file allows to reset PHY 88E1548 when attribute is set 0
476+
due to some abnormal PHY behavior.
477+
Expected behavior:
478+
When phy_reset is written 1, all PHY 88E1548 are released
479+
from the reset state, when 0 - are hold in reset state.
480+
481+
The files are read/write.
482+
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What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/mac_reset
484+
Date: May 2022
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KernelVersion: 5.19
486+
Contact: Vadim Pasternak <vadimpmellanox.com>
487+
Description: This file allows to reset ASIC MT52132 when attribute is set 0
488+
due to some abnormal ASIC behavior.
489+
Expected behavior:
490+
When mac_reset is written 1, the ASIC MT52132 is released
491+
from the reset state, when 0 - is hold in reset state.
492+
493+
The files are read/write.
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What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/qsfp_pwr_good
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Date: May 2022
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KernelVersion: 5.19
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Contact: Vadim Pasternak <vadimpmellanox.com>
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Description: This file shows QSFP ports power status. The value is set to 0
500+
when one of any QSFP ports is plugged. The value is set to 1 when
501+
there are no any QSFP ports are plugged.
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The possible values are:
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0 - Power good, 1 - Not power good.
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The files are read only.

‎Documentation/ABI/testing/sysfs-platform-intel-ifs‎

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@@ -0,0 +1,39 @@
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What: /sys/devices/virtual/misc/intel_ifs_<N>/run_test
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Date: April 21 2022
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KernelVersion: 5.19
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Contact: "Jithu Joseph" <jithu.joseph@intel.com>
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Description: Write <cpu#> to trigger IFS test for one online core.
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Note that the test is per core. The cpu# can be
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for any thread on the core. Running on one thread
8+
completes the test for the core containing that thread.
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Example: to test the core containing cpu5: echo 5 >
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/sys/devices/platform/intel_ifs.<N>/run_test
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What: /sys/devices/virtual/misc/intel_ifs_<N>/status
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Date: April 21 2022
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KernelVersion: 5.19
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Contact: "Jithu Joseph" <jithu.joseph@intel.com>
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Description: The status of the last test. It can be one of "pass", "fail"
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or "untested".
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What: /sys/devices/virtual/misc/intel_ifs_<N>/details
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Date: April 21 2022
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KernelVersion: 5.19
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Contact: "Jithu Joseph" <jithu.joseph@intel.com>
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Description: Additional information regarding the last test. The details file reports
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the hex value of the SCAN_STATUS MSR. Note that the error_code field
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may contain driver defined software code not defined in the Intel SDM.
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What: /sys/devices/virtual/misc/intel_ifs_<N>/image_version
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Date: April 21 2022
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KernelVersion: 5.19
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Contact: "Jithu Joseph" <jithu.joseph@intel.com>
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Description: Version (hexadecimal) of loaded IFS binary image. If no scan image
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is loaded reports "none".
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What: /sys/devices/virtual/misc/intel_ifs_<N>/reload
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Date: April 21 2022
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KernelVersion: 5.19
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Contact: "Jithu Joseph" <jithu.joseph@intel.com>
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Description: Write "1" (or "y" or "Y") to reload the IFS image from
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/lib/firmware/intel/ifs/ff-mm-ss.scan.

‎Documentation/x86/ifs.rst‎

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@@ -0,0 +1,2 @@
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.. SPDX-License-Identifier: GPL-2.0
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.. kernel-doc:: drivers/platform/x86/intel/ifs/ifs.h

‎Documentation/x86/index.rst‎

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@@ -36,6 +36,7 @@ x86-specific Documentation
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usb-legacy-support
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i386/index
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x86_64/index
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ifs
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sva
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sgx
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features

‎MAINTAINERS‎

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@@ -9863,6 +9863,14 @@ B: https://bugzilla.kernel.org
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T: git git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux.git
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F: drivers/idle/intel_idle.c
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INTEL IN FIELD SCAN (IFS) DEVICE
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M: Jithu Joseph <jithu.joseph@intel.com>
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R: Ashok Raj <ashok.raj@intel.com>
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R: Tony Luck <tony.luck@intel.com>
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S: Maintained
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F: drivers/platform/x86/intel/ifs
9872+
F: include/trace/events/intel_ifs.h
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98669874
INTEL INTEGRATED SENSOR HUB DRIVER
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M: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
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M: Jiri Kosina <jikos@kernel.org>

‎arch/x86/include/asm/cpu.h‎

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@@ -76,4 +76,22 @@ static inline void init_ia32_feat_ctl(struct cpuinfo_x86 *c) {}
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7777
extern __noendbr void cet_disable(void);
7878

79+
struct ucode_cpu_info;
80+
81+
int intel_cpu_collect_info(struct ucode_cpu_info *uci);
82+
83+
static inline bool intel_cpu_signatures_match(unsigned int s1, unsigned int p1,
84+
unsigned int s2, unsigned int p2)
85+
{
86+
if (s1 != s2)
87+
return false;
88+
89+
/* Processor flags are either both 0 ... */
90+
if (!p1 && !p2)
91+
return true;
92+
93+
/* ... or they intersect. */
94+
return p1 & p2;
95+
}
96+
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#endif /* _ASM_X86_CPU_H */

‎arch/x86/include/asm/msr-index.h‎

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@@ -76,6 +76,8 @@
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/* Abbreviated from Intel SDM name IA32_CORE_CAPABILITIES */
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#define MSR_IA32_CORE_CAPS 0x000000cf
79+
#define MSR_IA32_CORE_CAPS_INTEGRITY_CAPS_BIT 2
80+
#define MSR_IA32_CORE_CAPS_INTEGRITY_CAPS BIT(MSR_IA32_CORE_CAPS_INTEGRITY_CAPS_BIT)
7981
#define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT 5
8082
#define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT BIT(MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT)
8183

@@ -154,6 +156,11 @@
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#define MSR_IA32_POWER_CTL 0x000001fc
155157
#define MSR_IA32_POWER_CTL_BIT_EE 19
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159+
/* Abbreviated from Intel SDM name IA32_INTEGRITY_CAPABILITIES */
160+
#define MSR_INTEGRITY_CAPS 0x000002d9
161+
#define MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT 4
162+
#define MSR_INTEGRITY_CAPS_PERIODIC_BIST BIT(MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT)
163+
157164
#define MSR_LBR_NHM_FROM 0x00000680
158165
#define MSR_LBR_NHM_TO 0x000006c0
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#define MSR_LBR_CORE_FROM 0x00000040

‎arch/x86/include/uapi/asm/amd_hsmp.h‎

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Original file line numberDiff line numberDiff line change
@@ -31,9 +31,22 @@ enum hsmp_message_ids {
3131
HSMP_GET_CCLK_THROTTLE_LIMIT, /* 10h Get CCLK frequency limit in socket */
3232
HSMP_GET_C0_PERCENT, /* 11h Get average C0 residency in socket */
3333
HSMP_SET_NBIO_DPM_LEVEL, /* 12h Set max/min LCLK DPM Level for a given NBIO */
34-
/* 13h Reserved */
35-
HSMP_GET_DDR_BANDWIDTH = 0x14, /* 14h Get theoretical maximum and current DDR Bandwidth */
36-
HSMP_GET_TEMP_MONITOR, /* 15h Get per-DIMM temperature and refresh rates */
34+
HSMP_GET_NBIO_DPM_LEVEL, /* 13h Get LCLK DPM level min and max for a given NBIO */
35+
HSMP_GET_DDR_BANDWIDTH, /* 14h Get theoretical maximum and current DDR Bandwidth */
36+
HSMP_GET_TEMP_MONITOR, /* 15h Get socket temperature */
37+
HSMP_GET_DIMM_TEMP_RANGE, /* 16h Get per-DIMM temperature range and refresh rate */
38+
HSMP_GET_DIMM_POWER, /* 17h Get per-DIMM power consumption */
39+
HSMP_GET_DIMM_THERMAL, /* 18h Get per-DIMM thermal sensors */
40+
HSMP_GET_SOCKET_FREQ_LIMIT, /* 19h Get current active frequency per socket */
41+
HSMP_GET_CCLK_CORE_LIMIT, /* 1Ah Get CCLK frequency limit per core */
42+
HSMP_GET_RAILS_SVI, /* 1Bh Get SVI-based Telemetry for all rails */
43+
HSMP_GET_SOCKET_FMAX_FMIN, /* 1Ch Get Fmax and Fmin per socket */
44+
HSMP_GET_IOLINK_BANDWITH, /* 1Dh Get current bandwidth on IO Link */
45+
HSMP_GET_XGMI_BANDWITH, /* 1Eh Get current bandwidth on xGMI Link */
46+
HSMP_SET_GMI3_WIDTH, /* 1Fh Set max and min GMI3 Link width */
47+
HSMP_SET_PCI_RATE, /* 20h Control link rate on PCIe devices */
48+
HSMP_SET_POWER_MODE, /* 21h Select power efficiency profile policy */
49+
HSMP_SET_PSTATE_MAX_MIN, /* 22h Set the max and min DF P-State */
3750
HSMP_MSG_ID_MAX,
3851
};
3952

@@ -175,8 +188,12 @@ static const struct hsmp_msg_desc hsmp_msg_desc_table[] = {
175188
*/
176189
{1, 0, HSMP_SET},
177190

178-
/* RESERVED message */
179-
{0, 0, HSMP_RSVD},
191+
/*
192+
* HSMP_GET_NBIO_DPM_LEVEL, num_args = 1, response_sz = 1
193+
* input: args[0] = nbioid[23:16]
194+
* output: args[0] = max dpm level[15:8] + min dpm level[7:0]
195+
*/
196+
{1, 1, HSMP_GET},
180197

181198
/*
182199
* HSMP_GET_DDR_BANDWIDTH, num_args = 0, response_sz = 1
@@ -191,6 +208,93 @@ static const struct hsmp_msg_desc hsmp_msg_desc_table[] = {
191208
* [7:5] fractional part
192209
*/
193210
{0, 1, HSMP_GET},
211+
212+
/*
213+
* HSMP_GET_DIMM_TEMP_RANGE, num_args = 1, response_sz = 1
214+
* input: args[0] = DIMM address[7:0]
215+
* output: args[0] = refresh rate[3] + temperature range[2:0]
216+
*/
217+
{1, 1, HSMP_GET},
218+
219+
/*
220+
* HSMP_GET_DIMM_POWER, num_args = 1, response_sz = 1
221+
* input: args[0] = DIMM address[7:0]
222+
* output: args[0] = DIMM power in mW[31:17] + update rate in ms[16:8] +
223+
* DIMM address[7:0]
224+
*/
225+
{1, 1, HSMP_GET},
226+
227+
/*
228+
* HSMP_GET_DIMM_THERMAL, num_args = 1, response_sz = 1
229+
* input: args[0] = DIMM address[7:0]
230+
* output: args[0] = temperature in degree celcius[31:21] + update rate in ms[16:8] +
231+
* DIMM address[7:0]
232+
*/
233+
{1, 1, HSMP_GET},
234+
235+
/*
236+
* HSMP_GET_SOCKET_FREQ_LIMIT, num_args = 0, response_sz = 1
237+
* output: args[0] = frequency in MHz[31:16] + frequency source[15:0]
238+
*/
239+
{0, 1, HSMP_GET},
240+
241+
/*
242+
* HSMP_GET_CCLK_CORE_LIMIT, num_args = 1, response_sz = 1
243+
* input: args[0] = apic id [31:0]
244+
* output: args[0] = frequency in MHz[31:0]
245+
*/
246+
{1, 1, HSMP_GET},
247+
248+
/*
249+
* HSMP_GET_RAILS_SVI, num_args = 0, response_sz = 1
250+
* output: args[0] = power in mW[31:0]
251+
*/
252+
{0, 1, HSMP_GET},
253+
254+
/*
255+
* HSMP_GET_SOCKET_FMAX_FMIN, num_args = 0, response_sz = 1
256+
* output: args[0] = fmax in MHz[31:16] + fmin in MHz[15:0]
257+
*/
258+
{0, 1, HSMP_GET},
259+
260+
/*
261+
* HSMP_GET_IOLINK_BANDWITH, num_args = 1, response_sz = 1
262+
* input: args[0] = link id[15:8] + bw type[2:0]
263+
* output: args[0] = io bandwidth in Mbps[31:0]
264+
*/
265+
{1, 1, HSMP_GET},
266+
267+
/*
268+
* HSMP_GET_XGMI_BANDWITH, num_args = 1, response_sz = 1
269+
* input: args[0] = link id[15:8] + bw type[2:0]
270+
* output: args[0] = xgmi bandwidth in Mbps[31:0]
271+
*/
272+
{1, 1, HSMP_GET},
273+
274+
/*
275+
* HSMP_SET_GMI3_WIDTH, num_args = 1, response_sz = 0
276+
* input: args[0] = min link width[15:8] + max link width[7:0]
277+
*/
278+
{1, 0, HSMP_SET},
279+
280+
/*
281+
* HSMP_SET_PCI_RATE, num_args = 1, response_sz = 1
282+
* input: args[0] = link rate control value
283+
* output: args[0] = previous link rate control value
284+
*/
285+
{1, 1, HSMP_SET},
286+
287+
/*
288+
* HSMP_SET_POWER_MODE, num_args = 1, response_sz = 0
289+
* input: args[0] = power efficiency mode[2:0]
290+
*/
291+
{1, 0, HSMP_SET},
292+
293+
/*
294+
* HSMP_SET_PSTATE_MAX_MIN, num_args = 1, response_sz = 0
295+
* input: args[0] = min df pstate[15:8] + max df pstate[7:0]
296+
*/
297+
{1, 0, HSMP_SET},
194298
};
195299

196300
/* Reset to default packing */

‎arch/x86/kernel/cpu/intel.c‎

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@@ -184,6 +184,38 @@ static bool bad_spectre_microcode(struct cpuinfo_x86 *c)
184184
return false;
185185
}
186186

187+
int intel_cpu_collect_info(struct ucode_cpu_info *uci)
188+
{
189+
unsigned int val[2];
190+
unsigned int family, model;
191+
struct cpu_signature csig = { 0 };
192+
unsigned int eax, ebx, ecx, edx;
193+
194+
memset(uci, 0, sizeof(*uci));
195+
196+
eax = 0x00000001;
197+
ecx = 0;
198+
native_cpuid(&eax, &ebx, &ecx, &edx);
199+
csig.sig = eax;
200+
201+
family = x86_family(eax);
202+
model = x86_model(eax);
203+
204+
if (model >= 5 || family > 6) {
205+
/* get processor flags from MSR 0x17 */
206+
native_rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]);
207+
csig.pf = 1 << ((val[1] >> 18) & 7);
208+
}
209+
210+
csig.rev = intel_get_microcode_revision();
211+
212+
uci->cpu_sig = csig;
213+
uci->valid = 1;
214+
215+
return 0;
216+
}
217+
EXPORT_SYMBOL_GPL(intel_cpu_collect_info);
218+
187219
static void early_init_intel(struct cpuinfo_x86 *c)
188220
{
189221
u64 misc_enable;

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