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Yicong Yangacmel
Yicong Yang
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acmel
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perf arm-spe: Add support for SPE Data Source packet on HiSilicon HIP12
Add data source encoding for HiSilicon HIP12 and coresponding mapping to the perf's memory data source. This will help to synthesize the data and support upper layer tools like perf-mem and perf-c2c. Reviewed-by: Leo Yan <leo.yan@arm.com> Signed-off-by: Yicong Yang <yangyicong@hisilicon.com> Cc: CaiJingtao <caijingtao@huawei.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Ian Rogers <irogers@google.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: James Clark <james.clark@linaro.org> Cc: Jiri Olsa <jolsa@kernel.org> Cc: John Garry <john.g.garry@oracle.com> Cc: Jonathan Cameron <jonathan.cameron@huawei.com> Cc: Junhao He <hejunhao3@huawei.com> Cc: Leo Yan <leo.yan@linux.dev> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Will Deacon <will@kernel.org> Cc: Yushan Wang <wangyushan12@huawei.com> Cc: Zeng Tao <prime.zeng@hisilicon.com> Cc: xueshan2@huawei.com Link: https://lore.kernel.org/r/20250425033845.57671-3-yangyicong@huawei.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
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3 files changed

Lines changed: 115 additions & 0 deletions

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‎tools/arch/arm64/include/asm/cputype.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -129,6 +129,7 @@
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#define FUJITSU_CPU_PART_A64FX 0x001
130130

131131
#define HISI_CPU_PART_TSV110 0xD01
132+
#define HISI_CPU_PART_HIP12 0xD06
132133

133134
#define APPLE_CPU_PART_M1_ICESTORM 0x022
134135
#define APPLE_CPU_PART_M1_FIRESTORM 0x023
@@ -202,6 +203,7 @@
202203
#define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL)
203204
#define MIDR_FUJITSU_A64FX MIDR_CPU_MODEL(ARM_CPU_IMP_FUJITSU, FUJITSU_CPU_PART_A64FX)
204205
#define MIDR_HISI_TSV110 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TSV110)
206+
#define MIDR_HISI_HIP12 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_HIP12)
205207
#define MIDR_APPLE_M1_ICESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM)
206208
#define MIDR_APPLE_M1_FIRESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM)
207209
#define MIDR_APPLE_M1_ICESTORM_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM_PRO)

‎tools/perf/util/arm-spe-decoder/arm-spe-decoder.h‎

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -82,6 +82,23 @@ enum arm_spe_ampereone_data_source {
8282
ARM_SPE_AMPEREONE_L2D = 0x9,
8383
};
8484

85+
enum arm_spe_hisi_hip_data_source {
86+
ARM_SPE_HISI_HIP_PEER_CPU = 0,
87+
ARM_SPE_HISI_HIP_PEER_CPU_HITM = 1,
88+
ARM_SPE_HISI_HIP_L3 = 2,
89+
ARM_SPE_HISI_HIP_L3_HITM = 3,
90+
ARM_SPE_HISI_HIP_PEER_CLUSTER = 4,
91+
ARM_SPE_HISI_HIP_PEER_CLUSTER_HITM = 5,
92+
ARM_SPE_HISI_HIP_REMOTE_SOCKET = 6,
93+
ARM_SPE_HISI_HIP_REMOTE_SOCKET_HITM = 7,
94+
ARM_SPE_HISI_HIP_LOCAL_MEM = 8,
95+
ARM_SPE_HISI_HIP_REMOTE_MEM = 9,
96+
ARM_SPE_HISI_HIP_NC_DEV = 13,
97+
ARM_SPE_HISI_HIP_L2 = 16,
98+
ARM_SPE_HISI_HIP_L2_HITM = 17,
99+
ARM_SPE_HISI_HIP_L1 = 18,
100+
};
101+
85102
struct arm_spe_record {
86103
enum arm_spe_sample_type type;
87104
int err;

‎tools/perf/util/arm-spe.c‎

Lines changed: 96 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -571,6 +571,11 @@ static const struct midr_range ampereone_ds_encoding_cpus[] = {
571571
{},
572572
};
573573

574+
static const struct midr_range hisi_hip_ds_encoding_cpus[] = {
575+
MIDR_ALL_VERSIONS(MIDR_HISI_HIP12),
576+
{},
577+
};
578+
574579
static void arm_spe__sample_flags(struct arm_spe_queue *speq)
575580
{
576581
const struct arm_spe_record *record = &speq->decoder->record;
@@ -718,9 +723,100 @@ static void arm_spe__synth_data_source_ampereone(const struct arm_spe_record *re
718723
arm_spe__synth_data_source_common(&common_record, data_src);
719724
}
720725

726+
static void arm_spe__synth_data_source_hisi_hip(const struct arm_spe_record *record,
727+
union perf_mem_data_src *data_src)
728+
{
729+
/* Use common synthesis method to handle store operations */
730+
if (record->op & ARM_SPE_OP_ST) {
731+
arm_spe__synth_data_source_common(record, data_src);
732+
return;
733+
}
734+
735+
switch (record->source) {
736+
case ARM_SPE_HISI_HIP_PEER_CPU:
737+
data_src->mem_lvl = PERF_MEM_LVL_L2 | PERF_MEM_LVL_HIT;
738+
data_src->mem_lvl_num = PERF_MEM_LVLNUM_L2;
739+
data_src->mem_snoopx = PERF_MEM_SNOOPX_PEER;
740+
break;
741+
case ARM_SPE_HISI_HIP_PEER_CPU_HITM:
742+
data_src->mem_lvl = PERF_MEM_LVL_L2 | PERF_MEM_LVL_HIT;
743+
data_src->mem_lvl_num = PERF_MEM_LVLNUM_L2;
744+
data_src->mem_snoop = PERF_MEM_SNOOP_HITM;
745+
data_src->mem_snoopx = PERF_MEM_SNOOPX_PEER;
746+
break;
747+
case ARM_SPE_HISI_HIP_L3:
748+
data_src->mem_lvl = PERF_MEM_LVL_L3 | PERF_MEM_LVL_HIT;
749+
data_src->mem_lvl_num = PERF_MEM_LVLNUM_L3;
750+
data_src->mem_snoop = PERF_MEM_SNOOP_HIT;
751+
break;
752+
case ARM_SPE_HISI_HIP_L3_HITM:
753+
data_src->mem_lvl = PERF_MEM_LVL_L3 | PERF_MEM_LVL_HIT;
754+
data_src->mem_lvl_num = PERF_MEM_LVLNUM_L3;
755+
data_src->mem_snoop = PERF_MEM_SNOOP_HITM;
756+
break;
757+
case ARM_SPE_HISI_HIP_PEER_CLUSTER:
758+
data_src->mem_lvl = PERF_MEM_LVL_REM_CCE1 | PERF_MEM_LVL_HIT;
759+
data_src->mem_lvl_num = PERF_MEM_LVLNUM_L3;
760+
data_src->mem_snoopx = PERF_MEM_SNOOPX_PEER;
761+
break;
762+
case ARM_SPE_HISI_HIP_PEER_CLUSTER_HITM:
763+
data_src->mem_lvl = PERF_MEM_LVL_REM_CCE1 | PERF_MEM_LVL_HIT;
764+
data_src->mem_lvl_num = PERF_MEM_LVLNUM_L3;
765+
data_src->mem_snoop = PERF_MEM_SNOOP_HITM;
766+
data_src->mem_snoopx = PERF_MEM_SNOOPX_PEER;
767+
break;
768+
case ARM_SPE_HISI_HIP_REMOTE_SOCKET:
769+
data_src->mem_lvl = PERF_MEM_LVL_REM_CCE2;
770+
data_src->mem_lvl_num = PERF_MEM_LVLNUM_ANY_CACHE;
771+
data_src->mem_remote = PERF_MEM_REMOTE_REMOTE;
772+
data_src->mem_snoopx = PERF_MEM_SNOOPX_PEER;
773+
break;
774+
case ARM_SPE_HISI_HIP_REMOTE_SOCKET_HITM:
775+
data_src->mem_lvl = PERF_MEM_LVL_REM_CCE2;
776+
data_src->mem_lvl_num = PERF_MEM_LVLNUM_ANY_CACHE;
777+
data_src->mem_snoop = PERF_MEM_SNOOP_HITM;
778+
data_src->mem_remote = PERF_MEM_REMOTE_REMOTE;
779+
data_src->mem_snoopx = PERF_MEM_SNOOPX_PEER;
780+
break;
781+
case ARM_SPE_HISI_HIP_LOCAL_MEM:
782+
data_src->mem_lvl = PERF_MEM_LVL_LOC_RAM | PERF_MEM_LVL_HIT;
783+
data_src->mem_lvl_num = PERF_MEM_LVLNUM_RAM;
784+
data_src->mem_snoop = PERF_MEM_SNOOP_NONE;
785+
break;
786+
case ARM_SPE_HISI_HIP_REMOTE_MEM:
787+
data_src->mem_lvl = PERF_MEM_LVL_REM_RAM1 | PERF_MEM_LVL_HIT;
788+
data_src->mem_lvl_num = PERF_MEM_LVLNUM_RAM;
789+
data_src->mem_remote = PERF_MEM_REMOTE_REMOTE;
790+
break;
791+
case ARM_SPE_HISI_HIP_NC_DEV:
792+
data_src->mem_lvl = PERF_MEM_LVL_IO | PERF_MEM_LVL_HIT;
793+
data_src->mem_lvl_num = PERF_MEM_LVLNUM_IO;
794+
data_src->mem_snoop = PERF_MEM_SNOOP_NONE;
795+
break;
796+
case ARM_SPE_HISI_HIP_L2:
797+
data_src->mem_lvl = PERF_MEM_LVL_L2 | PERF_MEM_LVL_HIT;
798+
data_src->mem_lvl_num = PERF_MEM_LVLNUM_L2;
799+
data_src->mem_snoop = PERF_MEM_SNOOP_NONE;
800+
break;
801+
case ARM_SPE_HISI_HIP_L2_HITM:
802+
data_src->mem_lvl = PERF_MEM_LVL_L2 | PERF_MEM_LVL_HIT;
803+
data_src->mem_lvl_num = PERF_MEM_LVLNUM_L2;
804+
data_src->mem_snoop = PERF_MEM_SNOOP_HITM;
805+
break;
806+
case ARM_SPE_HISI_HIP_L1:
807+
data_src->mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_HIT;
808+
data_src->mem_lvl_num = PERF_MEM_LVLNUM_L1;
809+
data_src->mem_snoop = PERF_MEM_SNOOP_NONE;
810+
break;
811+
default:
812+
break;
813+
}
814+
}
815+
721816
static const struct data_source_handle data_source_handles[] = {
722817
DS(common_ds_encoding_cpus, data_source_common),
723818
DS(ampereone_ds_encoding_cpus, data_source_ampereone),
819+
DS(hisi_hip_ds_encoding_cpus, data_source_hisi_hip),
724820
};
725821

726822
static void arm_spe__synth_memory_level(const struct arm_spe_record *record,

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