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36 | 36 | #define CMDQ_THR_WAIT_TOKEN 0x30 |
37 | 37 | #define CMDQ_THR_PRIORITY 0x40 |
38 | 38 |
|
| 39 | +#define GCE_GCTL_VALUE 0x48 |
| 40 | + |
39 | 41 | #define CMDQ_THR_ACTIVE_SLOT_CYCLES 0x3200 |
40 | 42 | #define CMDQ_THR_ENABLED 0x1 |
41 | 43 | #define CMDQ_THR_DISABLED 0x0 |
@@ -76,11 +78,13 @@ struct cmdq { |
76 | 78 | struct clk *clock; |
77 | 79 | bool suspended; |
78 | 80 | u8 shift_pa; |
| 81 | + bool control_by_sw; |
79 | 82 | }; |
80 | 83 |
|
81 | 84 | struct gce_plat { |
82 | 85 | u32 thread_nr; |
83 | 86 | u8 shift; |
| 87 | + bool control_by_sw; |
84 | 88 | }; |
85 | 89 |
|
86 | 90 | u8 cmdq_get_shift_pa(struct mbox_chan *chan) |
@@ -121,6 +125,8 @@ static void cmdq_init(struct cmdq *cmdq) |
121 | 125 | int i; |
122 | 126 |
|
123 | 127 | WARN_ON(clk_enable(cmdq->clock) < 0); |
| 128 | + if (cmdq->control_by_sw) |
| 129 | + writel(0x7, cmdq->base + GCE_GCTL_VALUE); |
124 | 130 | writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base + CMDQ_THR_SLOT_CYCLES); |
125 | 131 | for (i = 0; i <= CMDQ_MAX_EVENT; i++) |
126 | 132 | writel(i, cmdq->base + CMDQ_SYNC_TOKEN_UPDATE); |
@@ -540,6 +546,7 @@ static int cmdq_probe(struct platform_device *pdev) |
540 | 546 |
|
541 | 547 | cmdq->thread_nr = plat_data->thread_nr; |
542 | 548 | cmdq->shift_pa = plat_data->shift; |
| 549 | + cmdq->control_by_sw = plat_data->control_by_sw; |
543 | 550 | cmdq->irq_mask = GENMASK(cmdq->thread_nr - 1, 0); |
544 | 551 | err = devm_request_irq(dev, cmdq->irq, cmdq_irq_handler, IRQF_SHARED, |
545 | 552 | "mtk_cmdq", cmdq); |
@@ -605,11 +612,14 @@ static const struct dev_pm_ops cmdq_pm_ops = { |
605 | 612 | static const struct gce_plat gce_plat_v2 = {.thread_nr = 16}; |
606 | 613 | static const struct gce_plat gce_plat_v3 = {.thread_nr = 24}; |
607 | 614 | static const struct gce_plat gce_plat_v4 = {.thread_nr = 24, .shift = 3}; |
| 615 | +static const struct gce_plat gce_plat_v5 = {.thread_nr = 24, .shift = 3, |
| 616 | + .control_by_sw = true}; |
608 | 617 |
|
609 | 618 | static const struct of_device_id cmdq_of_ids[] = { |
610 | 619 | {.compatible = "mediatek,mt8173-gce", .data = (void *)&gce_plat_v2}, |
611 | 620 | {.compatible = "mediatek,mt8183-gce", .data = (void *)&gce_plat_v3}, |
612 | 621 | {.compatible = "mediatek,mt6779-gce", .data = (void *)&gce_plat_v4}, |
| 622 | + {.compatible = "mediatek,mt8192-gce", .data = (void *)&gce_plat_v5}, |
613 | 623 | {} |
614 | 624 | }; |
615 | 625 |
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