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Merge tag 'drivers-5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC driver updates from Arnd Bergmann: "These are updates for drivers that are tied to a particular SoC, including the correspondig device tree bindings: - A couple of reset controller changes for unisoc, uniphier, renesas and zte platforms - memory controller driver fixes for omap and tegra - Rockchip io domain driver updates - Lots of updates for qualcomm platforms, mostly touching their firmware and power management drivers - Tegra FUSE and firmware driver updateѕ - Support for virtio transports in the SCMI firmware framework - cleanup of ixp4xx drivers, towards enabling multiplatform support and bringing it up to date with modern platforms - Minor updates for keystone, mediatek, omap, renesas" * tag 'drivers-5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (96 commits) reset: simple: remove ZTE details in Kconfig help soc: rockchip: io-domain: Remove unneeded semicolon soc: rockchip: io-domain: add rk3568 support dt-bindings: power: add rk3568-pmu-io-domain support bus: ixp4xx: return on error in ixp4xx_exp_probe() soc: renesas: Prefer memcpy() over strcpy() firmware: tegra: Stop using seq_get_buf() soc/tegra: fuse: Enable fuse clock on suspend for Tegra124 soc/tegra: fuse: Add runtime PM support soc/tegra: fuse: Clear fuse->clk on driver probe failure soc/tegra: pmc: Prevent racing with cpuilde driver soc/tegra: bpmp: Remove unused including <linux/version.h> dt-bindings: soc: ti: pruss: Add dma-coherent property soc: ti: Remove pm_runtime_irq_safe() usage for smartreflex soc: ti: pruss: Enable support for ICSSG subsystems on K3 AM64x SoCs dt-bindings: soc: ti: pruss: Update bindings for K3 AM64x SoCs firmware: arm_scmi: Use WARN_ON() to check configured transports firmware: arm_scmi: Fix boolconv.cocci warnings soc: mediatek: mmsys: Fix missing UFOE component in mt8173 table routing soc: mediatek: mmsys: add MT8365 support ...
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‎Documentation/devicetree/bindings/ata/intel,ixp4xx-compact-flash.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/ata/intel,ixp4xx-compact-flash.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Intel IXP4xx CompactFlash Card Controller
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maintainers:
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- Linus Walleij <linus.walleij@linaro.org>
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description: |
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The IXP4xx network processors have a CompactFlash interface that presents
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a CompactFlash card to the system as a true IDE (parallel ATA) device. The
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device is always connected to the expansion bus of the IXP4xx SoCs using one
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or two chip select areas and address translating logic on the board. The
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node must be placed inside a chip select node on the IXP4xx expansion bus.
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properties:
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compatible:
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const: intel,ixp4xx-compact-flash
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reg:
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items:
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- description: Command interface registers
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- description: Control interface registers
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interrupts:
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maxItems: 1
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required:
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- compatible
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- reg
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- interrupts
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allOf:
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- $ref: pata-common.yaml#
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/irq.h>
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bus@c4000000 {
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compatible = "intel,ixp43x-expansion-bus-controller", "syscon";
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reg = <0xc4000000 0x1000>;
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native-endian;
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <0 0x0 0x50000000 0x01000000>, <1 0x0 0x51000000 0x01000000>;
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dma-ranges = <0 0x0 0x50000000 0x01000000>, <1 0x0 0x51000000 0x01000000>;
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ide@1,0 {
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compatible = "intel,ixp4xx-compact-flash";
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reg = <1 0x00000000 0x1000>, <1 0x00040000 0x1000>;
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interrupt-parent = <&gpio0>;
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interrupts = <12 IRQ_TYPE_EDGE_RISING>;
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};
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};
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...

‎Documentation/devicetree/bindings/bus/intel,ixp4xx-expansion-bus-controller.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/bus/intel,ixp4xx-expansion-bus-controller.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Intel IXP4xx Expansion Bus Controller
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description: |
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The IXP4xx expansion bus controller handles access to devices on the
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memory-mapped expansion bus on the Intel IXP4xx family of system on chips,
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including IXP42x, IXP43x, IXP45x and IXP46x.
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maintainers:
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- Linus Walleij <linus.walleij@linaro.org>
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properties:
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$nodename:
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pattern: '^bus@[0-9a-f]+$'
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compatible:
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items:
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- enum:
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- intel,ixp42x-expansion-bus-controller
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- intel,ixp43x-expansion-bus-controller
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- intel,ixp45x-expansion-bus-controller
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- intel,ixp46x-expansion-bus-controller
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- const: syscon
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reg:
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description: Control registers for the expansion bus, these are not
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inside the memory range handled by the expansion bus.
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maxItems: 1
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native-endian:
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$ref: /schemas/types.yaml#/definitions/flag
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description: The IXP4xx has a peculiar MMIO access scheme, as it changes
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the access pattern for words (swizzling) on the bus depending on whether
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the SoC is running in big-endian or little-endian mode. Thus the
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registers must always be accessed using native endianness.
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"#address-cells":
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description: |
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The first cell is the chip select number.
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The second cell is the address offset within the bank.
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const: 2
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"#size-cells":
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const: 1
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ranges: true
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dma-ranges: true
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patternProperties:
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"^.*@[0-7],[0-9a-f]+$":
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description: Devices attached to chip selects are represented as
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subnodes.
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type: object
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properties:
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intel,ixp4xx-eb-t1:
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description: Address timing, extend address phase with n cycles.
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$ref: /schemas/types.yaml#/definitions/uint32
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maximum: 3
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intel,ixp4xx-eb-t2:
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description: Setup chip select timing, extend setup phase with n cycles.
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$ref: /schemas/types.yaml#/definitions/uint32
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maximum: 3
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intel,ixp4xx-eb-t3:
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description: Strobe timing, extend strobe phase with n cycles.
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$ref: /schemas/types.yaml#/definitions/uint32
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maximum: 15
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intel,ixp4xx-eb-t4:
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description: Hold timing, extend hold phase with n cycles.
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$ref: /schemas/types.yaml#/definitions/uint32
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maximum: 3
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intel,ixp4xx-eb-t5:
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description: Recovery timing, extend recovery phase with n cycles.
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$ref: /schemas/types.yaml#/definitions/uint32
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maximum: 15
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intel,ixp4xx-eb-cycle-type:
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description: The type of cycles to use on the expansion bus for this
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chip select. 0 = Intel cycles, 1 = Motorola cycles, 2 = HPI cycles.
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [0, 1, 2]
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intel,ixp4xx-eb-byte-access-on-halfword:
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description: Allow byte read access on half word devices.
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [0, 1]
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intel,ixp4xx-eb-hpi-hrdy-pol-high:
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description: Set HPI HRDY polarity to active high when using HPI.
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [0, 1]
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intel,ixp4xx-eb-mux-address-and-data:
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description: Multiplex address and data on the data bus.
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [0, 1]
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intel,ixp4xx-eb-ahb-split-transfers:
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description: Enable AHB split transfers.
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [0, 1]
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intel,ixp4xx-eb-write-enable:
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description: Enable write cycles.
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [0, 1]
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intel,ixp4xx-eb-byte-access:
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description: Expansion bus uses only 8 bits. The default is to use
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16 bits.
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [0, 1]
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required:
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- compatible
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- reg
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- native-endian
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- "#address-cells"
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- "#size-cells"
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- ranges
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- dma-ranges
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/irq.h>
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bus@50000000 {
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compatible = "intel,ixp42x-expansion-bus-controller", "syscon";
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reg = <0xc4000000 0x28>;
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native-endian;
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <0 0x0 0x50000000 0x01000000>,
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<1 0x0 0x51000000 0x01000000>;
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dma-ranges = <0 0x0 0x50000000 0x01000000>,
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<1 0x0 0x51000000 0x01000000>;
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flash@0,0 {
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compatible = "intel,ixp4xx-flash", "cfi-flash";
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bank-width = <2>;
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reg = <0 0x00000000 0x1000000>;
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intel,ixp4xx-eb-t3 = <3>;
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intel,ixp4xx-eb-cycle-type = <0>;
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intel,ixp4xx-eb-byte-access-on-halfword = <1>;
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intel,ixp4xx-eb-write-enable = <1>;
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intel,ixp4xx-eb-byte-access = <0>;
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};
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serial@1,0 {
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compatible = "exar,xr16l2551", "ns8250";
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reg = <1 0x00000000 0x10>;
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interrupt-parent = <&gpio0>;
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interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
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clock-frequency = <1843200>;
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intel,ixp4xx-eb-t3 = <3>;
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intel,ixp4xx-eb-cycle-type = <1>;
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intel,ixp4xx-eb-write-enable = <1>;
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intel,ixp4xx-eb-byte-access = <1>;
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};
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};

‎Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt‎

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"fsl,imx53-sdma"
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"fsl,imx6q-sdma"
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"fsl,imx7d-sdma"
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"fsl,imx6ul-sdma"
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"fsl,imx8mq-sdma"
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"fsl,imx8mm-sdma"
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"fsl,imx8mn-sdma"

‎Documentation/devicetree/bindings/firmware/arm,scmi.yaml‎

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- description: SCMI compliant firmware with ARM SMC/HVC transport
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items:
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- const: arm,scmi-smc
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- description: SCMI compliant firmware with SCMI Virtio transport.
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The virtio transport only supports a single device.
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items:
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- const: arm,scmi-virtio
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interrupts:
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description:
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Each sub-node represents a protocol supported. If the platform
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supports a dedicated communication channel for a particular protocol,
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then the corresponding transport properties must be present.
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The virtio transport does not support a dedicated communication channel.
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properties:
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reg:
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required:
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- compatible
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- shmem
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if:
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properties:
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required:
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- mboxes
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- shmem
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else:
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if:
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then:
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required:
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- arm,smc-id
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- shmem
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examples:
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- |

‎Documentation/devicetree/bindings/power/qcom,rpmpd.yaml‎

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- qcom,sc8180x-rpmhpd
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- qcom,sdm845-rpmhpd
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- qcom,sdx55-rpmhpd
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- qcom,sm6115-rpmpd
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- qcom,sm8150-rpmhpd
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- qcom,sm8250-rpmhpd
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- qcom,sm8350-rpmhpd

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