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Merge tag 'stm32-mp25-for-v6.5-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into soc/newsoc
STM32 STM32MP25 for v6.5, round 1 Highlights: ---------- STM32MP25 family is composed of 4 SoCs defined as following: -STM32MP251: common part composed of 1*Cortex-A35, common peripherals like SDMMC, UART, SPI, I2C, PCIe, USB3, parallel and DSI display, 1*ETH ... -STM32MP253: STM32MP251 + 1*Cortex-A35 (dual CPU), a second ETH, CAN-FD and LVDS display. -STM32MP255: STM32MP253 + GPU/AI and video encode/decode. -STM32MP257: STM32MP255 + ETH TSN switch (2+1 ports). A second diversity layer exists for security features/A35 frequency: -STM32MP25xY, "Y" gives information: -Y = A means A35@1.2GHz + no cryp IP and no secure boot. -Y = C means A35@1.2GHz + cryp IP and secure boot. -Y = D means A35@1.5GHz + no cryp IP and no secure boot. -Y = F means A35@1.5GHz + cryp IP and secure boot. This PR adds the STM32MP257F EV1 board support. This board embeds a STM32MP257FAI SoC, with 4GB of DDR4, TSN switch (2+1 ports), 2*USB typeA, 1*USB2 typeC, SNOR OctoSPI, mini PCIe, STPMIC2 for power distribution ... * tag 'stm32-mp25-for-v6.5-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: (44 commits) MAINTAINERS: add entry for ARM/STM32 ARCHITECTURE arm64: defconfig: enable ARCH_STM32 and STM32 serial driver arm64: dts: st: add stm32mp257f-ev1 board support dt-bindings: stm32: document stm32mp257f-ev1 board arm64: dts: st: introduce stm32mp25 pinctrl files arm64: dts: st: introduce stm32mp25 SoCs family arm64: introduce STM32 family on Armv8 architecture dt-bindings: stm32: add st,stm32mp25-syscfg compatible for syscon pinctrl: stm32: add stm32mp257 pinctrl support dt-bindings: pinctrl: stm32: support for stm32mp257 and additional packages ARM: dts: stm32: fix i2s endpoint format property for stm32mp15xx-dkx ARM: dts: stm32: Fix audio routing on STM32MP15xx DHCOM PDK2 ARM: dts: stm32: add required supplies of ov5640 in stm32mp157c-ev1 ARM: dts: stm32: Update to generic ADC channel binding on DHSOM systems ARM: dts: stm32: adopt generic iio bindings for adc channels on dhcor-testbench ARM: dts: stm32: adopt generic iio bindings for adc channels on dhcor-drc ARM: dts: stm32: adopt generic iio bindings for adc channels on emstamp-argon ARM: dts: stm32: adopt generic iio bindings for adc channels on stm32mp157c-ed1 ARM: dts: stm32: enable adc on stm32mp15xx-dkx boards ARM: dts: stm32: add vrefint support to adc2 on stm32mp15 ... Link: https://lore.kernel.org/r/080fc303-45c1-6cc0-4c5e-694e730896a6@foss.st.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2 parents 425d827 + c9cb7e7 commit 868a11b

54 files changed

Lines changed: 4389 additions & 108 deletions

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‎Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml‎

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -15,12 +15,13 @@ properties:
1515
oneOf:
1616
- items:
1717
- enum:
18-
- st,stm32mp157-syscfg
19-
- st,stm32mp151-pwr-mcu
20-
- st,stm32-syscfg
2118
- st,stm32-power-config
19+
- st,stm32-syscfg
2220
- st,stm32-tamp
2321
- st,stm32f4-gcan
22+
- st,stm32mp151-pwr-mcu
23+
- st,stm32mp157-syscfg
24+
- st,stm32mp25-syscfg
2425
- const: syscon
2526
- items:
2627
- const: st,stm32-tamp

‎Documentation/devicetree/bindings/arm/stm32/stm32.yaml‎

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -155,6 +155,18 @@ properties:
155155
- const: seeed,stm32mp157c-odyssey-som
156156
- const: st,stm32mp157
157157

158+
- description: Phytec STM32MP1 SoM based Boards
159+
items:
160+
- const: phytec,phycore-stm32mp1-3
161+
- const: phytec,phycore-stm32mp157c-som
162+
- const: st,stm32mp157
163+
164+
- description: ST STM32MP257 based Boards
165+
items:
166+
- enum:
167+
- st,stm32mp257f-ev1
168+
- const: st,stm32mp257
169+
158170
additionalProperties: true
159171

160172
...

‎Documentation/devicetree/bindings/display/st,stm32-dsi.yaml‎

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Original file line numberDiff line numberDiff line change
@@ -74,8 +74,6 @@ properties:
7474
- const: 2
7575

7676
required:
77-
- "#address-cells"
78-
- "#size-cells"
7977
- compatible
8078
- reg
8179
- clocks

‎Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -27,6 +27,8 @@ properties:
2727
- st,stm32mp135-pinctrl
2828
- st,stm32mp157-pinctrl
2929
- st,stm32mp157-z-pinctrl
30+
- st,stm32mp257-pinctrl
31+
- st,stm32mp257-z-pinctrl
3032

3133
'#address-cells':
3234
const: 1
@@ -56,7 +58,7 @@ properties:
5658
Indicates the SOC package used.
5759
More details in include/dt-bindings/pinctrl/stm32-pinfunc.h
5860
$ref: /schemas/types.yaml#/definitions/uint32
59-
enum: [1, 2, 4, 8]
61+
enum: [0x1, 0x2, 0x4, 0x8, 0x100, 0x400, 0x800]
6062

6163
patternProperties:
6264
'^gpio@[0-9a-f]*$':

‎MAINTAINERS‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2854,6 +2854,7 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32.git stm32-nex
28542854
F: arch/arm/boot/dts/stm32*
28552855
F: arch/arm/mach-stm32/
28562856
F: drivers/clocksource/armv7m_systick.c
2857+
F: arch/arm64/boot/dts/st/
28572858
N: stm32
28582859
N: stm
28592860

‎arch/arm/boot/dts/Makefile‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1266,7 +1266,8 @@ dtb-$(CONFIG_ARCH_STM32) += \
12661266
stm32mp157c-ev1.dtb \
12671267
stm32mp157c-ev1-scmi.dtb \
12681268
stm32mp157c-lxa-mc1.dtb \
1269-
stm32mp157c-odyssey.dtb
1269+
stm32mp157c-odyssey.dtb \
1270+
stm32mp157c-phycore-stm32mp1-3.dtb
12701271
dtb-$(CONFIG_MACH_SUN4I) += \
12711272
sun4i-a10-a1000.dtb \
12721273
sun4i-a10-ba10-tvbox.dtb \

‎arch/arm/boot/dts/stm32f469-disco.dts‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -160,7 +160,7 @@
160160
};
161161
};
162162

163-
panel-dsi@0 {
163+
panel@0 {
164164
compatible = "orisetech,otm8009a";
165165
reg = <0>; /* dsi virtual channel (0..3) */
166166
reset-gpios = <&gpioh 7 GPIO_ACTIVE_LOW>;
@@ -179,7 +179,7 @@
179179
status = "okay";
180180

181181
port {
182-
ltdc_out_dsi: endpoint@0 {
182+
ltdc_out_dsi: endpoint {
183183
remote-endpoint = <&dsi_in>;
184184
};
185185
};

‎arch/arm/boot/dts/stm32f746.dtsi‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -515,7 +515,7 @@
515515
crc: crc@40023000 {
516516
compatible = "st,stm32f7-crc";
517517
reg = <0x40023000 0x400>;
518-
clocks = <&rcc 0 12>;
518+
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(CRC)>;
519519
status = "disabled";
520520
};
521521

‎arch/arm/boot/dts/stm32h750i-art-pi.dts‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -208,7 +208,7 @@
208208
dmas = <&dmamux1 45 0x400 0x05>,
209209
<&dmamux1 46 0x400 0x05>;
210210
dma-names = "rx", "tx";
211-
st,hw-flow-ctrl;
211+
uart-has-rtscts;
212212
status = "okay";
213213

214214
bluetooth {

‎arch/arm/boot/dts/stm32mp15-pinctrl.dtsi‎

Lines changed: 231 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -341,6 +341,56 @@
341341
};
342342
};
343343

344+
ethernet0_rgmii_pins_d: rgmii-3 {
345+
pins1 {
346+
pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
347+
<STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
348+
<STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
349+
<STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
350+
<STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */
351+
<STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */
352+
<STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
353+
bias-disable;
354+
drive-push-pull;
355+
slew-rate = <2>;
356+
};
357+
pins2 {
358+
pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */
359+
bias-disable;
360+
drive-push-pull;
361+
slew-rate = <0>;
362+
};
363+
pins3 {
364+
pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
365+
<STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
366+
<STM32_PINMUX('H', 6, AF11)>, /* ETH_RGMII_RXD2 */
367+
<STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */
368+
<STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
369+
<STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
370+
bias-disable;
371+
};
372+
};
373+
374+
ethernet0_rgmii_sleep_pins_d: rgmii-sleep-3 {
375+
pins1 {
376+
pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
377+
<STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
378+
<STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */
379+
<STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
380+
<STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
381+
<STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */
382+
<STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
383+
<STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
384+
<STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */
385+
<STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
386+
<STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
387+
<STM32_PINMUX('H', 6, ANALOG)>, /* ETH_RGMII_RXD2 */
388+
<STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */
389+
<STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
390+
<STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
391+
};
392+
};
393+
344394
ethernet0_rmii_pins_a: rmii-0 {
345395
pins1 {
346396
pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */
@@ -1441,6 +1491,30 @@
14411491
};
14421492
};
14431493

1494+
sai2b_pins_d: sai2b-3 {
1495+
pins1 {
1496+
pinmux = <STM32_PINMUX('H', 2, AF10)>, /* SAI2_SCK_B */
1497+
<STM32_PINMUX('C', 0, AF8)>, /* SAI2_FS_B */
1498+
<STM32_PINMUX('H', 3, AF10)>; /* SAI2_MCLK_B */
1499+
slew-rate = <0>;
1500+
drive-push-pull;
1501+
bias-disable;
1502+
};
1503+
pins2 {
1504+
pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */
1505+
bias-disable;
1506+
};
1507+
};
1508+
1509+
sai2b_sleep_pins_d: sai2b-sleep-3 {
1510+
pins1 {
1511+
pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* SAI2_SCK_B */
1512+
<STM32_PINMUX('C', 0, ANALOG)>, /* SAI2_FS_B */
1513+
<STM32_PINMUX('H', 3, ANALOG)>, /* SAI2_MCLK_B */
1514+
<STM32_PINMUX('F', 11, ANALOG)>; /* SAI2_SD_B */
1515+
};
1516+
};
1517+
14441518
sai4a_pins_a: sai4a-0 {
14451519
pins {
14461520
pinmux = <STM32_PINMUX('B', 5, AF10)>; /* SAI4_SD_A */
@@ -1522,6 +1596,60 @@
15221596
};
15231597
};
15241598

1599+
sdmmc1_b4_pins_b: sdmmc1-b4-1 {
1600+
pins1 {
1601+
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
1602+
<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
1603+
<STM32_PINMUX('E', 6, AF8)>, /* SDMMC1_D2 */
1604+
<STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
1605+
<STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
1606+
slew-rate = <1>;
1607+
drive-push-pull;
1608+
bias-disable;
1609+
};
1610+
pins2 {
1611+
pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
1612+
slew-rate = <2>;
1613+
drive-push-pull;
1614+
bias-disable;
1615+
};
1616+
};
1617+
1618+
sdmmc1_b4_od_pins_b: sdmmc1-b4-od-1 {
1619+
pins1 {
1620+
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
1621+
<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
1622+
<STM32_PINMUX('E', 6, AF8)>, /* SDMMC1_D2 */
1623+
<STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */
1624+
slew-rate = <1>;
1625+
drive-push-pull;
1626+
bias-disable;
1627+
};
1628+
pins2 {
1629+
pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
1630+
slew-rate = <2>;
1631+
drive-push-pull;
1632+
bias-disable;
1633+
};
1634+
pins3 {
1635+
pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
1636+
slew-rate = <1>;
1637+
drive-open-drain;
1638+
bias-disable;
1639+
};
1640+
};
1641+
1642+
sdmmc1_b4_sleep_pins_b: sdmmc1-b4-sleep-1 {
1643+
pins {
1644+
pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
1645+
<STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
1646+
<STM32_PINMUX('E', 6, ANALOG)>, /* SDMMC1_D2 */
1647+
<STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
1648+
<STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
1649+
<STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
1650+
};
1651+
};
1652+
15251653
sdmmc1_dir_pins_a: sdmmc1-dir-0 {
15261654
pins1 {
15271655
pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
@@ -1759,6 +1887,27 @@
17591887
};
17601888
};
17611889

1890+
sdmmc2_d47_pins_e: sdmmc2-d47-4 {
1891+
pins {
1892+
pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
1893+
<STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
1894+
<STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */
1895+
<STM32_PINMUX('D', 3, AF9)>; /* SDMMC2_D7 */
1896+
slew-rate = <1>;
1897+
drive-push-pull;
1898+
bias-pull-up;
1899+
};
1900+
};
1901+
1902+
sdmmc2_d47_sleep_pins_e: sdmmc2-d47-sleep-4 {
1903+
pins {
1904+
pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
1905+
<STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */
1906+
<STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */
1907+
<STM32_PINMUX('D', 3, ANALOG)>; /* SDMMC2_D7 */
1908+
};
1909+
};
1910+
17621911
sdmmc3_b4_pins_a: sdmmc3-b4-0 {
17631912
pins1 {
17641913
pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */
@@ -2124,6 +2273,33 @@
21242273
};
21252274
};
21262275

2276+
usart1_pins_a: usart1-0 {
2277+
pins1 {
2278+
pinmux = <STM32_PINMUX('A', 12, AF7)>; /* USART1_RTS */
2279+
bias-disable;
2280+
drive-push-pull;
2281+
slew-rate = <0>;
2282+
};
2283+
pins2 {
2284+
pinmux = <STM32_PINMUX('A', 11, AF7)>; /* USART1_CTS_NSS */
2285+
bias-disable;
2286+
};
2287+
};
2288+
2289+
usart1_idle_pins_a: usart1-idle-0 {
2290+
pins1 {
2291+
pinmux = <STM32_PINMUX('A', 12, ANALOG)>, /* USART1_RTS */
2292+
<STM32_PINMUX('A', 11, AF7)>; /* USART1_CTS_NSS */
2293+
};
2294+
};
2295+
2296+
usart1_sleep_pins_a: usart1-sleep-0 {
2297+
pins {
2298+
pinmux = <STM32_PINMUX('A', 12, ANALOG)>, /* USART1_RTS */
2299+
<STM32_PINMUX('A', 11, ANALOG)>; /* USART1_CTS_NSS */
2300+
};
2301+
};
2302+
21272303
usart2_pins_a: usart2-0 {
21282304
pins1 {
21292305
pinmux = <STM32_PINMUX('F', 5, AF7)>, /* USART2_TX */
@@ -2226,6 +2402,23 @@
22262402
};
22272403
};
22282404

2405+
usart3_idle_pins_a: usart3-idle-0 {
2406+
pins1 {
2407+
pinmux = <STM32_PINMUX('B', 10, ANALOG)>; /* USART3_TX */
2408+
};
2409+
pins2 {
2410+
pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */
2411+
bias-disable;
2412+
};
2413+
};
2414+
2415+
usart3_sleep_pins_a: usart3-sleep-0 {
2416+
pins {
2417+
pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
2418+
<STM32_PINMUX('B', 12, ANALOG)>; /* USART3_RX */
2419+
};
2420+
};
2421+
22292422
usart3_pins_b: usart3-1 {
22302423
pins1 {
22312424
pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
@@ -2463,4 +2656,42 @@
24632656
bias-disable;
24642657
};
24652658
};
2659+
2660+
spi1_sleep_pins_a: spi1-sleep-0 {
2661+
pins {
2662+
pinmux = <STM32_PINMUX('Z', 0, ANALOG)>, /* SPI1_SCK */
2663+
<STM32_PINMUX('Z', 1, ANALOG)>, /* SPI1_MISO */
2664+
<STM32_PINMUX('Z', 2, ANALOG)>; /* SPI1_MOSI */
2665+
};
2666+
};
2667+
2668+
usart1_pins_b: usart1-1 {
2669+
pins1 {
2670+
pinmux = <STM32_PINMUX('Z', 7, AF7)>; /* USART1_TX */
2671+
bias-disable;
2672+
drive-push-pull;
2673+
slew-rate = <0>;
2674+
};
2675+
pins2 {
2676+
pinmux = <STM32_PINMUX('Z', 6, AF7)>; /* USART1_RX */
2677+
bias-disable;
2678+
};
2679+
};
2680+
2681+
usart1_idle_pins_b: usart1-idle-1 {
2682+
pins1 {
2683+
pinmux = <STM32_PINMUX('Z', 7, ANALOG)>; /* USART1_TX */
2684+
};
2685+
pins2 {
2686+
pinmux = <STM32_PINMUX('Z', 6, AF7)>; /* USART1_RX */
2687+
bias-disable;
2688+
};
2689+
};
2690+
2691+
usart1_sleep_pins_b: usart1-sleep-1 {
2692+
pins {
2693+
pinmux = <STM32_PINMUX('Z', 7, ANALOG)>, /* USART1_TX */
2694+
<STM32_PINMUX('Z', 6, ANALOG)>; /* USART1_RX */
2695+
};
2696+
};
24662697
};

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