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3 | 3 | * Copyright 2022 Toradex |
4 | 4 | */ |
5 | 5 |
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6 | | -/* TODO: Audio Codec */ |
| 6 | +/ { |
| 7 | + sound { |
| 8 | + compatible = "simple-audio-card"; |
| 9 | + simple-audio-card,bitclock-master = <&codec_dai>; |
| 10 | + simple-audio-card,format = "i2s"; |
| 11 | + simple-audio-card,frame-master = <&codec_dai>; |
| 12 | + simple-audio-card,mclk-fs = <256>; |
| 13 | + simple-audio-card,name = "imx8mp-wm8904"; |
| 14 | + simple-audio-card,routing = |
| 15 | + "Headphone Jack", "HPOUTL", |
| 16 | + "Headphone Jack", "HPOUTR", |
| 17 | + "IN2L", "Line In Jack", |
| 18 | + "IN2R", "Line In Jack", |
| 19 | + "Headphone Jack", "MICBIAS", |
| 20 | + "IN1L", "Headphone Jack"; |
| 21 | + simple-audio-card,widgets = |
| 22 | + "Microphone", "Headphone Jack", |
| 23 | + "Headphone", "Headphone Jack", |
| 24 | + "Line", "Line In Jack"; |
| 25 | + |
| 26 | + codec_dai: simple-audio-card,codec { |
| 27 | + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1>; |
| 28 | + sound-dai = <&wm8904_1a>; |
| 29 | + }; |
| 30 | + |
| 31 | + simple-audio-card,cpu { |
| 32 | + sound-dai = <&sai1>; |
| 33 | + }; |
| 34 | + }; |
| 35 | +}; |
7 | 36 |
|
8 | 37 | &backlight { |
9 | 38 | power-supply = <®_3p3v>; |
|
64 | 93 | &i2c4 { |
65 | 94 | status = "okay"; |
66 | 95 |
|
67 | | - /* TODO: Audio Codec */ |
| 96 | + /* Audio Codec */ |
| 97 | + wm8904_1a: audio-codec@1a { |
| 98 | + compatible = "wlf,wm8904"; |
| 99 | + reg = <0x1a>; |
| 100 | + pinctrl-names = "default"; |
| 101 | + pinctrl-0 = <&pinctrl_sai1>; |
| 102 | + #sound-dai-cells = <0>; |
| 103 | + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1>; |
| 104 | + clock-names = "mclk"; |
| 105 | + AVDD-supply = <®_1p8v>; |
| 106 | + CPVDD-supply = <®_1p8v>; |
| 107 | + DBVDD-supply = <®_1p8v>; |
| 108 | + DCVDD-supply = <®_1p8v>; |
| 109 | + MICVDD-supply = <®_1p8v>; |
| 110 | + }; |
68 | 111 | }; |
69 | 112 |
|
70 | 113 | /* Verdin PCIE_1 */ |
|
95 | 138 | vin-supply = <®_3p3v>; |
96 | 139 | }; |
97 | 140 |
|
98 | | -/* TODO: Verdin I2S_1 */ |
| 141 | +/* Verdin I2S_1 */ |
| 142 | +&sai1 { |
| 143 | + assigned-clocks = <&clk IMX8MP_CLK_SAI1>; |
| 144 | + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; |
| 145 | + assigned-clock-rates = <24576000>; |
| 146 | + fsl,sai-mclk-direction-output; |
| 147 | + status = "okay"; |
| 148 | +}; |
99 | 149 |
|
100 | 150 | /* Verdin UART_1 */ |
101 | 151 | &uart1 { |
|
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