@@ -1160,8 +1160,14 @@ PMUV3_INIT_SIMPLE(armv8_cortex_a75)
11601160PMUV3_INIT_SIMPLE (armv8_cortex_a76 )
11611161PMUV3_INIT_SIMPLE (armv8_cortex_a77 )
11621162PMUV3_INIT_SIMPLE (armv8_cortex_a78 )
1163+ PMUV3_INIT_SIMPLE (armv9_cortex_a510 )
1164+ PMUV3_INIT_SIMPLE (armv9_cortex_a710 )
1165+ PMUV3_INIT_SIMPLE (armv8_cortex_x1 )
1166+ PMUV3_INIT_SIMPLE (armv9_cortex_x2 )
11631167PMUV3_INIT_SIMPLE (armv8_neoverse_e1 )
11641168PMUV3_INIT_SIMPLE (armv8_neoverse_n1 )
1169+ PMUV3_INIT_SIMPLE (armv9_neoverse_n2 )
1170+ PMUV3_INIT_SIMPLE (armv8_neoverse_v1 )
11651171
11661172PMUV3_INIT_SIMPLE (armv8_nvidia_carmel )
11671173PMUV3_INIT_SIMPLE (armv8_nvidia_denver )
@@ -1222,8 +1228,14 @@ static const struct of_device_id armv8_pmu_of_device_ids[] = {
12221228 {.compatible = "arm,cortex-a76-pmu" , .data = armv8_cortex_a76_pmu_init },
12231229 {.compatible = "arm,cortex-a77-pmu" , .data = armv8_cortex_a77_pmu_init },
12241230 {.compatible = "arm,cortex-a78-pmu" , .data = armv8_cortex_a78_pmu_init },
1231+ {.compatible = "arm,cortex-a510-pmu" , .data = armv9_cortex_a510_pmu_init },
1232+ {.compatible = "arm,cortex-a710-pmu" , .data = armv9_cortex_a710_pmu_init },
1233+ {.compatible = "arm,cortex-x1-pmu" , .data = armv8_cortex_x1_pmu_init },
1234+ {.compatible = "arm,cortex-x2-pmu" , .data = armv9_cortex_x2_pmu_init },
12251235 {.compatible = "arm,neoverse-e1-pmu" , .data = armv8_neoverse_e1_pmu_init },
12261236 {.compatible = "arm,neoverse-n1-pmu" , .data = armv8_neoverse_n1_pmu_init },
1237+ {.compatible = "arm,neoverse-n2-pmu" , .data = armv9_neoverse_n2_pmu_init },
1238+ {.compatible = "arm,neoverse-v1-pmu" , .data = armv8_neoverse_v1_pmu_init },
12271239 {.compatible = "cavium,thunder-pmu" , .data = armv8_thunder_pmu_init },
12281240 {.compatible = "brcm,vulcan-pmu" , .data = armv8_vulcan_pmu_init },
12291241 {.compatible = "nvidia,carmel-pmu" , .data = armv8_nvidia_carmel_pmu_init },
0 commit comments