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akhilr-nvWolfram Sang
akhilr-nv
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Wolfram Sang
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i2c: tegra: Use separate variables for fast and fastplus
The current implementation uses a single value of THIGH, TLOW and setup hold time for both fast and fastplus. But these values can be different for each speed mode and should be using separate variables. Split the variables used for fast and fast plus mode. Signed-off-by: Akhil R <akhilrajeev@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
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Lines changed: 73 additions & 46 deletions

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‎drivers/i2c/busses/i2c-tegra.c‎

Lines changed: 73 additions & 46 deletions
Original file line numberDiff line numberDiff line change
@@ -196,12 +196,16 @@ enum msg_end_type {
196196
* @has_apb_dma: Support of APBDMA on corresponding Tegra chip.
197197
* @tlow_std_mode: Low period of the clock in standard mode.
198198
* @thigh_std_mode: High period of the clock in standard mode.
199-
* @tlow_fast_fastplus_mode: Low period of the clock in fast/fast-plus modes.
200-
* @thigh_fast_fastplus_mode: High period of the clock in fast/fast-plus modes.
199+
* @tlow_fast_mode: Low period of the clock in fast mode.
200+
* @thigh_fast_mode: High period of the clock in fast mode.
201+
* @tlow_fastplus_mode: Low period of the clock in fast-plus mode.
202+
* @thigh_fastplus_mode: High period of the clock in fast-plus mode.
201203
* @setup_hold_time_std_mode: Setup and hold time for start and stop conditions
202204
* in standard mode.
203-
* @setup_hold_time_fast_fast_plus_mode: Setup and hold time for start and stop
204-
* conditions in fast/fast-plus modes.
205+
* @setup_hold_time_fast_mode: Setup and hold time for start and stop
206+
* conditions in fast mode.
207+
* @setup_hold_time_fastplus_mode: Setup and hold time for start and stop
208+
* conditions in fast-plus mode.
205209
* @setup_hold_time_hs_mode: Setup and hold time for start and stop conditions
206210
* in HS mode.
207211
* @has_interface_timing_reg: Has interface timing register to program the tuned
@@ -224,10 +228,13 @@ struct tegra_i2c_hw_feature {
224228
bool has_apb_dma;
225229
u32 tlow_std_mode;
226230
u32 thigh_std_mode;
227-
u32 tlow_fast_fastplus_mode;
228-
u32 thigh_fast_fastplus_mode;
231+
u32 tlow_fast_mode;
232+
u32 thigh_fast_mode;
233+
u32 tlow_fastplus_mode;
234+
u32 thigh_fastplus_mode;
229235
u32 setup_hold_time_std_mode;
230-
u32 setup_hold_time_fast_fast_plus_mode;
236+
u32 setup_hold_time_fast_mode;
237+
u32 setup_hold_time_fastplus_mode;
231238
u32 setup_hold_time_hs_mode;
232239
bool has_interface_timing_reg;
233240
};
@@ -677,25 +684,21 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
677684
if (IS_VI(i2c_dev))
678685
tegra_i2c_vi_init(i2c_dev);
679686

680-
switch (t->bus_freq_hz) {
681-
case I2C_MAX_STANDARD_MODE_FREQ + 1 ... I2C_MAX_FAST_MODE_PLUS_FREQ:
682-
default:
683-
tlow = i2c_dev->hw->tlow_fast_fastplus_mode;
684-
thigh = i2c_dev->hw->thigh_fast_fastplus_mode;
685-
tsu_thd = i2c_dev->hw->setup_hold_time_fast_fast_plus_mode;
686-
687-
if (t->bus_freq_hz > I2C_MAX_FAST_MODE_FREQ)
688-
non_hs_mode = i2c_dev->hw->clk_divisor_fast_plus_mode;
689-
else
690-
non_hs_mode = i2c_dev->hw->clk_divisor_fast_mode;
691-
break;
692-
693-
case 0 ... I2C_MAX_STANDARD_MODE_FREQ:
687+
if (t->bus_freq_hz <= I2C_MAX_STANDARD_MODE_FREQ) {
694688
tlow = i2c_dev->hw->tlow_std_mode;
695689
thigh = i2c_dev->hw->thigh_std_mode;
696690
tsu_thd = i2c_dev->hw->setup_hold_time_std_mode;
697691
non_hs_mode = i2c_dev->hw->clk_divisor_std_mode;
698-
break;
692+
} else if (t->bus_freq_hz <= I2C_MAX_FAST_MODE_FREQ) {
693+
tlow = i2c_dev->hw->tlow_fast_mode;
694+
thigh = i2c_dev->hw->thigh_fast_mode;
695+
tsu_thd = i2c_dev->hw->setup_hold_time_fast_mode;
696+
non_hs_mode = i2c_dev->hw->clk_divisor_fast_mode;
697+
} else {
698+
tlow = i2c_dev->hw->tlow_fastplus_mode;
699+
thigh = i2c_dev->hw->thigh_fastplus_mode;
700+
tsu_thd = i2c_dev->hw->setup_hold_time_fastplus_mode;
701+
non_hs_mode = i2c_dev->hw->clk_divisor_fast_plus_mode;
699702
}
700703

701704
/* make sure clock divisor programmed correctly */
@@ -1496,10 +1499,13 @@ static const struct tegra_i2c_hw_feature tegra20_i2c_hw = {
14961499
.has_apb_dma = true,
14971500
.tlow_std_mode = 0x4,
14981501
.thigh_std_mode = 0x2,
1499-
.tlow_fast_fastplus_mode = 0x4,
1500-
.thigh_fast_fastplus_mode = 0x2,
1502+
.tlow_fast_mode = 0x4,
1503+
.thigh_fast_mode = 0x2,
1504+
.tlow_fastplus_mode = 0x4,
1505+
.thigh_fastplus_mode = 0x2,
15011506
.setup_hold_time_std_mode = 0x0,
1502-
.setup_hold_time_fast_fast_plus_mode = 0x0,
1507+
.setup_hold_time_fast_mode = 0x0,
1508+
.setup_hold_time_fastplus_mode = 0x0,
15031509
.setup_hold_time_hs_mode = 0x0,
15041510
.has_interface_timing_reg = false,
15051511
};
@@ -1521,10 +1527,13 @@ static const struct tegra_i2c_hw_feature tegra30_i2c_hw = {
15211527
.has_apb_dma = true,
15221528
.tlow_std_mode = 0x4,
15231529
.thigh_std_mode = 0x2,
1524-
.tlow_fast_fastplus_mode = 0x4,
1525-
.thigh_fast_fastplus_mode = 0x2,
1530+
.tlow_fast_mode = 0x4,
1531+
.thigh_fast_mode = 0x2,
1532+
.tlow_fastplus_mode = 0x4,
1533+
.thigh_fastplus_mode = 0x2,
15261534
.setup_hold_time_std_mode = 0x0,
1527-
.setup_hold_time_fast_fast_plus_mode = 0x0,
1535+
.setup_hold_time_fast_mode = 0x0,
1536+
.setup_hold_time_fastplus_mode = 0x0,
15281537
.setup_hold_time_hs_mode = 0x0,
15291538
.has_interface_timing_reg = false,
15301539
};
@@ -1546,10 +1555,13 @@ static const struct tegra_i2c_hw_feature tegra114_i2c_hw = {
15461555
.has_apb_dma = true,
15471556
.tlow_std_mode = 0x4,
15481557
.thigh_std_mode = 0x2,
1549-
.tlow_fast_fastplus_mode = 0x4,
1550-
.thigh_fast_fastplus_mode = 0x2,
1558+
.tlow_fast_mode = 0x4,
1559+
.thigh_fast_mode = 0x2,
1560+
.tlow_fastplus_mode = 0x4,
1561+
.thigh_fastplus_mode = 0x2,
15511562
.setup_hold_time_std_mode = 0x0,
1552-
.setup_hold_time_fast_fast_plus_mode = 0x0,
1563+
.setup_hold_time_fast_mode = 0x0,
1564+
.setup_hold_time_fastplus_mode = 0x0,
15531565
.setup_hold_time_hs_mode = 0x0,
15541566
.has_interface_timing_reg = false,
15551567
};
@@ -1571,10 +1583,13 @@ static const struct tegra_i2c_hw_feature tegra124_i2c_hw = {
15711583
.has_apb_dma = true,
15721584
.tlow_std_mode = 0x4,
15731585
.thigh_std_mode = 0x2,
1574-
.tlow_fast_fastplus_mode = 0x4,
1575-
.thigh_fast_fastplus_mode = 0x2,
1586+
.tlow_fast_mode = 0x4,
1587+
.thigh_fast_mode = 0x2,
1588+
.tlow_fastplus_mode = 0x4,
1589+
.thigh_fastplus_mode = 0x2,
15761590
.setup_hold_time_std_mode = 0x0,
1577-
.setup_hold_time_fast_fast_plus_mode = 0x0,
1591+
.setup_hold_time_fast_mode = 0x0,
1592+
.setup_hold_time_fastplus_mode = 0x0,
15781593
.setup_hold_time_hs_mode = 0x0,
15791594
.has_interface_timing_reg = true,
15801595
};
@@ -1596,10 +1611,13 @@ static const struct tegra_i2c_hw_feature tegra210_i2c_hw = {
15961611
.has_apb_dma = true,
15971612
.tlow_std_mode = 0x4,
15981613
.thigh_std_mode = 0x2,
1599-
.tlow_fast_fastplus_mode = 0x4,
1600-
.thigh_fast_fastplus_mode = 0x2,
1614+
.tlow_fast_mode = 0x4,
1615+
.thigh_fast_mode = 0x2,
1616+
.tlow_fastplus_mode = 0x4,
1617+
.thigh_fastplus_mode = 0x2,
16011618
.setup_hold_time_std_mode = 0,
1602-
.setup_hold_time_fast_fast_plus_mode = 0,
1619+
.setup_hold_time_fast_mode = 0,
1620+
.setup_hold_time_fastplus_mode = 0,
16031621
.setup_hold_time_hs_mode = 0,
16041622
.has_interface_timing_reg = true,
16051623
};
@@ -1621,10 +1639,13 @@ static const struct tegra_i2c_hw_feature tegra186_i2c_hw = {
16211639
.has_apb_dma = false,
16221640
.tlow_std_mode = 0x4,
16231641
.thigh_std_mode = 0x3,
1624-
.tlow_fast_fastplus_mode = 0x4,
1625-
.thigh_fast_fastplus_mode = 0x2,
1642+
.tlow_fast_mode = 0x4,
1643+
.thigh_fast_mode = 0x2,
1644+
.tlow_fastplus_mode = 0x4,
1645+
.thigh_fastplus_mode = 0x2,
16261646
.setup_hold_time_std_mode = 0,
1627-
.setup_hold_time_fast_fast_plus_mode = 0,
1647+
.setup_hold_time_fast_mode = 0,
1648+
.setup_hold_time_fastplus_mode = 0,
16281649
.setup_hold_time_hs_mode = 0,
16291650
.has_interface_timing_reg = true,
16301651
};
@@ -1646,10 +1667,13 @@ static const struct tegra_i2c_hw_feature tegra194_i2c_hw = {
16461667
.has_apb_dma = false,
16471668
.tlow_std_mode = 0x8,
16481669
.thigh_std_mode = 0x7,
1649-
.tlow_fast_fastplus_mode = 0x2,
1650-
.thigh_fast_fastplus_mode = 0x2,
1670+
.tlow_fast_mode = 0x2,
1671+
.thigh_fast_mode = 0x2,
1672+
.tlow_fastplus_mode = 0x2,
1673+
.thigh_fastplus_mode = 0x2,
16511674
.setup_hold_time_std_mode = 0x08080808,
1652-
.setup_hold_time_fast_fast_plus_mode = 0x02020202,
1675+
.setup_hold_time_fast_mode = 0x02020202,
1676+
.setup_hold_time_fastplus_mode = 0x02020202,
16531677
.setup_hold_time_hs_mode = 0x090909,
16541678
.has_interface_timing_reg = true,
16551679
};
@@ -1671,10 +1695,13 @@ static const struct tegra_i2c_hw_feature tegra256_i2c_hw = {
16711695
.has_apb_dma = false,
16721696
.tlow_std_mode = 0x8,
16731697
.thigh_std_mode = 0x7,
1674-
.tlow_fast_fastplus_mode = 0x3,
1675-
.thigh_fast_fastplus_mode = 0x3,
1698+
.tlow_fast_mode = 0x3,
1699+
.thigh_fast_mode = 0x3,
1700+
.tlow_fastplus_mode = 0x3,
1701+
.thigh_fastplus_mode = 0x3,
16761702
.setup_hold_time_std_mode = 0x08080808,
1677-
.setup_hold_time_fast_fast_plus_mode = 0x02020202,
1703+
.setup_hold_time_fast_mode = 0x02020202,
1704+
.setup_hold_time_fastplus_mode = 0x02020202,
16781705
.setup_hold_time_hs_mode = 0x090909,
16791706
.has_interface_timing_reg = true,
16801707
};

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