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johnharr-inteljohnharr-intel
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drm/i915/guc: Fix confused register capture list creation
The GuC has a completely separate engine class enum when referring to register capture lists, which combines render and compute. The driver was using the 'normal' GuC specific engine class enum instead. That meant that it thought it was defining a capture list for compute engines, the list was actually being applied to the GSC engine. And if a platform didn't have a render engine, then it would get no compute register captures at all. Fix that. Signed-off-by: John Harrison <John.C.Harrison@Intel.com> Reviewed-by: Alan Previn <alan.previn.teres.alexis@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230512013544.3367606-1-John.C.Harrison@Intel.com
1 parent db2ce1a commit 8ba3ba9

3 files changed

Lines changed: 72 additions & 34 deletions

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‎drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c‎

Lines changed: 35 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -643,6 +643,39 @@ static void guc_init_golden_context(struct intel_guc *guc)
643643
GEM_BUG_ON(guc->ads_golden_ctxt_size != total_size);
644644
}
645645

646+
static u32 guc_get_capture_engine_mask(struct iosys_map *info_map, u32 capture_class)
647+
{
648+
u32 mask;
649+
650+
switch (capture_class) {
651+
case GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE:
652+
mask = info_map_read(info_map, engine_enabled_masks[GUC_RENDER_CLASS]);
653+
mask |= info_map_read(info_map, engine_enabled_masks[GUC_COMPUTE_CLASS]);
654+
break;
655+
656+
case GUC_CAPTURE_LIST_CLASS_VIDEO:
657+
mask = info_map_read(info_map, engine_enabled_masks[GUC_VIDEO_CLASS]);
658+
break;
659+
660+
case GUC_CAPTURE_LIST_CLASS_VIDEOENHANCE:
661+
mask = info_map_read(info_map, engine_enabled_masks[GUC_VIDEOENHANCE_CLASS]);
662+
break;
663+
664+
case GUC_CAPTURE_LIST_CLASS_BLITTER:
665+
mask = info_map_read(info_map, engine_enabled_masks[GUC_BLITTER_CLASS]);
666+
break;
667+
668+
case GUC_CAPTURE_LIST_CLASS_GSC_OTHER:
669+
mask = info_map_read(info_map, engine_enabled_masks[GUC_GSC_OTHER_CLASS]);
670+
break;
671+
672+
default:
673+
mask = 0;
674+
}
675+
676+
return mask;
677+
}
678+
646679
static int
647680
guc_capture_prep_lists(struct intel_guc *guc)
648681
{
@@ -678,9 +711,10 @@ guc_capture_prep_lists(struct intel_guc *guc)
678711

679712
for (i = 0; i < GUC_CAPTURE_LIST_INDEX_MAX; i++) {
680713
for (j = 0; j < GUC_MAX_ENGINE_CLASSES; j++) {
714+
u32 engine_mask = guc_get_capture_engine_mask(&info_map, j);
681715

682716
/* null list if we dont have said engine or list */
683-
if (!info_map_read(&info_map, engine_enabled_masks[j])) {
717+
if (!engine_mask) {
684718
if (ads_is_mapped) {
685719
ads_blob_write(guc, ads.capture_class[i][j], null_ggtt);
686720
ads_blob_write(guc, ads.capture_instance[i][j], null_ggtt);

‎drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c‎

Lines changed: 28 additions & 33 deletions
Original file line numberDiff line numberDiff line change
@@ -174,35 +174,31 @@ static const struct __guc_mmio_reg_descr empty_regs_list[] = {
174174
/* List of lists */
175175
static const struct __guc_mmio_reg_descr_group gen8_lists[] = {
176176
MAKE_REGLIST(gen8_global_regs, PF, GLOBAL, 0),
177-
MAKE_REGLIST(gen8_rc_class_regs, PF, ENGINE_CLASS, GUC_RENDER_CLASS),
178-
MAKE_REGLIST(gen8_rc_inst_regs, PF, ENGINE_INSTANCE, GUC_RENDER_CLASS),
179-
MAKE_REGLIST(gen8_rc_class_regs, PF, ENGINE_CLASS, GUC_COMPUTE_CLASS),
180-
MAKE_REGLIST(gen8_rc_inst_regs, PF, ENGINE_INSTANCE, GUC_COMPUTE_CLASS),
181-
MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_VIDEO_CLASS),
182-
MAKE_REGLIST(gen8_vd_inst_regs, PF, ENGINE_INSTANCE, GUC_VIDEO_CLASS),
183-
MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_VIDEOENHANCE_CLASS),
184-
MAKE_REGLIST(gen8_vec_inst_regs, PF, ENGINE_INSTANCE, GUC_VIDEOENHANCE_CLASS),
185-
MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_BLITTER_CLASS),
186-
MAKE_REGLIST(gen8_blt_inst_regs, PF, ENGINE_INSTANCE, GUC_BLITTER_CLASS),
187-
MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_GSC_OTHER_CLASS),
188-
MAKE_REGLIST(empty_regs_list, PF, ENGINE_INSTANCE, GUC_GSC_OTHER_CLASS),
177+
MAKE_REGLIST(gen8_rc_class_regs, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE),
178+
MAKE_REGLIST(gen8_rc_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE),
179+
MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_VIDEO),
180+
MAKE_REGLIST(gen8_vd_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_VIDEO),
181+
MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_VIDEOENHANCE),
182+
MAKE_REGLIST(gen8_vec_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_VIDEOENHANCE),
183+
MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_BLITTER),
184+
MAKE_REGLIST(gen8_blt_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_BLITTER),
185+
MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_GSC_OTHER),
186+
MAKE_REGLIST(empty_regs_list, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_GSC_OTHER),
189187
{}
190188
};
191189

192190
static const struct __guc_mmio_reg_descr_group xe_lp_lists[] = {
193191
MAKE_REGLIST(xe_lp_global_regs, PF, GLOBAL, 0),
194-
MAKE_REGLIST(xe_lp_rc_class_regs, PF, ENGINE_CLASS, GUC_RENDER_CLASS),
195-
MAKE_REGLIST(gen8_rc_inst_regs, PF, ENGINE_INSTANCE, GUC_RENDER_CLASS),
196-
MAKE_REGLIST(xe_lp_rc_class_regs, PF, ENGINE_CLASS, GUC_COMPUTE_CLASS),
197-
MAKE_REGLIST(gen8_rc_inst_regs, PF, ENGINE_INSTANCE, GUC_COMPUTE_CLASS),
198-
MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_VIDEO_CLASS),
199-
MAKE_REGLIST(gen8_vd_inst_regs, PF, ENGINE_INSTANCE, GUC_VIDEO_CLASS),
200-
MAKE_REGLIST(xe_lp_vec_class_regs, PF, ENGINE_CLASS, GUC_VIDEOENHANCE_CLASS),
201-
MAKE_REGLIST(gen8_vec_inst_regs, PF, ENGINE_INSTANCE, GUC_VIDEOENHANCE_CLASS),
202-
MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_BLITTER_CLASS),
203-
MAKE_REGLIST(gen8_blt_inst_regs, PF, ENGINE_INSTANCE, GUC_BLITTER_CLASS),
204-
MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_GSC_OTHER_CLASS),
205-
MAKE_REGLIST(xe_lp_gsc_inst_regs, PF, ENGINE_INSTANCE, GUC_GSC_OTHER_CLASS),
192+
MAKE_REGLIST(xe_lp_rc_class_regs, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE),
193+
MAKE_REGLIST(gen8_rc_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE),
194+
MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_VIDEO),
195+
MAKE_REGLIST(gen8_vd_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_VIDEO),
196+
MAKE_REGLIST(xe_lp_vec_class_regs, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_VIDEOENHANCE),
197+
MAKE_REGLIST(gen8_vec_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_VIDEOENHANCE),
198+
MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_BLITTER),
199+
MAKE_REGLIST(gen8_blt_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_BLITTER),
200+
MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_GSC_OTHER),
201+
MAKE_REGLIST(xe_lp_gsc_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_GSC_OTHER),
206202
{}
207203
};
208204

@@ -310,7 +306,8 @@ guc_capture_alloc_steered_lists(struct intel_guc *guc,
310306

311307
/* steered registers currently only exist for the render-class */
312308
list = guc_capture_get_one_list(lists, GUC_CAPTURE_LIST_INDEX_PF,
313-
GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS, GUC_RENDER_CLASS);
309+
GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS,
310+
GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE);
314311
/* skip if extlists was previously allocated */
315312
if (!list || guc->capture->extlists)
316313
return;
@@ -400,17 +397,15 @@ static const char *
400397
__stringify_engclass(u32 class)
401398
{
402399
switch (class) {
403-
case GUC_RENDER_CLASS:
404-
return "Render";
405-
case GUC_VIDEO_CLASS:
400+
case GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE:
401+
return "Render/Compute";
402+
case GUC_CAPTURE_LIST_CLASS_VIDEO:
406403
return "Video";
407-
case GUC_VIDEOENHANCE_CLASS:
404+
case GUC_CAPTURE_LIST_CLASS_VIDEOENHANCE:
408405
return "VideoEnhance";
409-
case GUC_BLITTER_CLASS:
406+
case GUC_CAPTURE_LIST_CLASS_BLITTER:
410407
return "Blitter";
411-
case GUC_COMPUTE_CLASS:
412-
return "Compute";
413-
case GUC_GSC_OTHER_CLASS:
408+
case GUC_CAPTURE_LIST_CLASS_GSC_OTHER:
414409
return "GSC-Other";
415410
default:
416411
break;

‎drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h‎

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -411,6 +411,15 @@ enum guc_capture_type {
411411
GUC_CAPTURE_LIST_TYPE_MAX,
412412
};
413413

414+
/* Class indecies for capture_class and capture_instance arrays */
415+
enum {
416+
GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE = 0,
417+
GUC_CAPTURE_LIST_CLASS_VIDEO = 1,
418+
GUC_CAPTURE_LIST_CLASS_VIDEOENHANCE = 2,
419+
GUC_CAPTURE_LIST_CLASS_BLITTER = 3,
420+
GUC_CAPTURE_LIST_CLASS_GSC_OTHER = 4,
421+
};
422+
414423
/* GuC Additional Data Struct */
415424
struct guc_ads {
416425
struct guc_mmio_reg_set reg_state_list[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];

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