44 *
55 * Tests for Hyper-V features enablement
66 */
7+ #define USE_GUEST_ASSERT_PRINTF 1
8+
79#include <asm/kvm_para.h>
810#include <linux/kvm_para.h>
911#include <stdint.h>
@@ -53,16 +55,21 @@ static void guest_msr(struct msr_data *msr)
5355 vector = rdmsr_safe (msr -> idx , & msr_val );
5456
5557 if (msr -> fault_expected )
56- GUEST_ASSERT_3 (vector == GP_VECTOR , msr -> idx , vector , GP_VECTOR );
58+ __GUEST_ASSERT (vector == GP_VECTOR ,
59+ "Expected #GP on %sMSR(0x%x), got vector '0x%x'" ,
60+ msr -> idx , msr -> write ? "WR" : "RD" , vector );
5761 else
58- GUEST_ASSERT_3 (!vector , msr -> idx , vector , 0 );
62+ __GUEST_ASSERT (!vector ,
63+ "Expected success on %sMSR(0x%x), got vector '0x%x'" ,
64+ msr -> idx , msr -> write ? "WR" : "RD" , vector );
5965
6066 if (vector || is_write_only_msr (msr -> idx ))
6167 goto done ;
6268
6369 if (msr -> write )
64- GUEST_ASSERT_3 (msr_val == msr -> write_val , msr -> idx ,
65- msr_val , msr -> write_val );
70+ __GUEST_ASSERT (!vector ,
71+ "WRMSR(0x%x) to '0x%llx', RDMSR read '0x%llx'" ,
72+ msr -> idx , msr -> write_val , msr_val );
6673
6774 /* Invariant TSC bit appears when TSC invariant control MSR is written to */
6875 if (msr -> idx == HV_X64_MSR_TSC_INVARIANT_CONTROL ) {
@@ -82,7 +89,7 @@ static void guest_hcall(vm_vaddr_t pgs_gpa, struct hcall_data *hcall)
8289 u64 res , input , output ;
8390 uint8_t vector ;
8491
85- GUEST_ASSERT (hcall -> control );
92+ GUEST_ASSERT_NE (hcall -> control , 0 );
8693
8794 wrmsr (HV_X64_MSR_GUEST_OS_ID , HYPERV_LINUX_OS_ID );
8895 wrmsr (HV_X64_MSR_HYPERCALL , pgs_gpa );
@@ -96,10 +103,14 @@ static void guest_hcall(vm_vaddr_t pgs_gpa, struct hcall_data *hcall)
96103
97104 vector = __hyperv_hypercall (hcall -> control , input , output , & res );
98105 if (hcall -> ud_expected ) {
99- GUEST_ASSERT_2 (vector == UD_VECTOR , hcall -> control , vector );
106+ __GUEST_ASSERT (vector == UD_VECTOR ,
107+ "Expected #UD for control '%u', got vector '0x%x'" ,
108+ hcall -> control , vector );
100109 } else {
101- GUEST_ASSERT_2 (!vector , hcall -> control , vector );
102- GUEST_ASSERT_2 (res == hcall -> expect , hcall -> expect , res );
110+ __GUEST_ASSERT (!vector ,
111+ "Expected no exception for control '%u', got vector '0x%x'" ,
112+ hcall -> control , vector );
113+ GUEST_ASSERT_EQ (res , hcall -> expect );
103114 }
104115
105116 GUEST_DONE ();
@@ -495,7 +506,7 @@ static void guest_test_msrs_access(void)
495506
496507 switch (get_ucall (vcpu , & uc )) {
497508 case UCALL_ABORT :
498- REPORT_GUEST_ASSERT_3 (uc , "MSR = %lx, arg1 = %lx, arg2 = %lx" );
509+ REPORT_GUEST_ASSERT (uc );
499510 return ;
500511 case UCALL_DONE :
501512 break ;
@@ -665,7 +676,7 @@ static void guest_test_hcalls_access(void)
665676
666677 switch (get_ucall (vcpu , & uc )) {
667678 case UCALL_ABORT :
668- REPORT_GUEST_ASSERT_2 (uc , "arg1 = %lx, arg2 = %lx" );
679+ REPORT_GUEST_ASSERT (uc );
669680 return ;
670681 case UCALL_DONE :
671682 break ;
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