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MIPS: Remove unused shadow GPR support from vector irq setup
Using shadow GPRs for vectored interrupts has never been used, time to remove it. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
1 parent 682fb5b commit 8e18039

1 file changed

Lines changed: 27 additions & 61 deletions

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arch/mips/kernel/traps.c

Lines changed: 27 additions & 61 deletions
Original file line numberDiff line numberDiff line change
@@ -2055,105 +2055,71 @@ static void do_default_vi(void)
20552055
panic("Caught unexpected vectored interrupt.");
20562056
}
20572057

2058-
static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
2058+
void *set_vi_handler(int n, vi_handler_t addr)
20592059
{
2060+
extern const u8 except_vec_vi[];
2061+
extern const u8 except_vec_vi_ori[], except_vec_vi_end[];
2062+
extern const u8 rollback_except_vec_vi[];
20602063
unsigned long handler;
20612064
unsigned long old_handler = vi_handlers[n];
20622065
int srssets = current_cpu_data.srsets;
20632066
u16 *h;
20642067
unsigned char *b;
2068+
const u8 *vec_start;
2069+
int ori_offset;
2070+
int handler_len;
20652071

20662072
BUG_ON(!cpu_has_veic && !cpu_has_vint);
20672073

20682074
if (addr == NULL) {
20692075
handler = (unsigned long) do_default_vi;
2070-
srs = 0;
20712076
} else
20722077
handler = (unsigned long) addr;
20732078
vi_handlers[n] = handler;
20742079

20752080
b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
20762081

2077-
if (srs >= srssets)
2078-
panic("Shadow register set %d not supported", srs);
2079-
20802082
if (cpu_has_veic) {
20812083
if (board_bind_eic_interrupt)
2082-
board_bind_eic_interrupt(n, srs);
2084+
board_bind_eic_interrupt(n, 0);
20832085
} else if (cpu_has_vint) {
20842086
/* SRSMap is only defined if shadow sets are implemented */
20852087
if (srssets > 1)
2086-
change_c0_srsmap(0xf << n*4, srs << n*4);
2088+
change_c0_srsmap(0xf << n*4, 0 << n*4);
20872089
}
20882090

2089-
if (srs == 0) {
2090-
/*
2091-
* If no shadow set is selected then use the default handler
2092-
* that does normal register saving and standard interrupt exit
2093-
*/
2094-
extern const u8 except_vec_vi[];
2095-
extern const u8 except_vec_vi_ori[], except_vec_vi_end[];
2096-
extern const u8 rollback_except_vec_vi[];
2097-
const u8 *vec_start = using_rollback_handler() ?
2098-
rollback_except_vec_vi : except_vec_vi;
2091+
vec_start = using_rollback_handler() ? rollback_except_vec_vi :
2092+
except_vec_vi;
20992093
#if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN)
2100-
const int ori_offset = except_vec_vi_ori - vec_start + 2;
2094+
ori_offset = except_vec_vi_ori - vec_start + 2;
21012095
#else
2102-
const int ori_offset = except_vec_vi_ori - vec_start;
2096+
ori_offset = except_vec_vi_ori - vec_start;
21032097
#endif
2104-
const int handler_len = except_vec_vi_end - vec_start;
2105-
2106-
if (handler_len > VECTORSPACING) {
2107-
/*
2108-
* Sigh... panicing won't help as the console
2109-
* is probably not configured :(
2110-
*/
2111-
panic("VECTORSPACING too small");
2112-
}
2098+
handler_len = except_vec_vi_end - vec_start;
21132099

2114-
set_handler(((unsigned long)b - ebase), vec_start,
2115-
#ifdef CONFIG_CPU_MICROMIPS
2116-
(handler_len - 1));
2117-
#else
2118-
handler_len);
2119-
#endif
2120-
/* insert offset into vi_handlers[] */
2121-
h = (u16 *)(b + ori_offset);
2122-
*h = n * sizeof(handler);
2123-
local_flush_icache_range((unsigned long)b,
2124-
(unsigned long)(b+handler_len));
2125-
}
2126-
else {
2100+
if (handler_len > VECTORSPACING) {
21272101
/*
2128-
* In other cases jump directly to the interrupt handler. It
2129-
* is the handler's responsibility to save registers if required
2130-
* (eg hi/lo) and return from the exception using "eret".
2102+
* Sigh... panicing won't help as the console
2103+
* is probably not configured :(
21312104
*/
2132-
u32 insn;
2105+
panic("VECTORSPACING too small");
2106+
}
21332107

2134-
h = (u16 *)b;
2135-
/* j handler */
2108+
set_handler(((unsigned long)b - ebase), vec_start,
21362109
#ifdef CONFIG_CPU_MICROMIPS
2137-
insn = 0xd4000000 | (((u32)handler & 0x07ffffff) >> 1);
2110+
(handler_len - 1));
21382111
#else
2139-
insn = 0x08000000 | (((u32)handler & 0x0fffffff) >> 2);
2112+
handler_len);
21402113
#endif
2141-
h[0] = (insn >> 16) & 0xffff;
2142-
h[1] = insn & 0xffff;
2143-
h[2] = 0;
2144-
h[3] = 0;
2145-
local_flush_icache_range((unsigned long)b,
2146-
(unsigned long)(b+8));
2147-
}
2114+
/* insert offset into vi_handlers[] */
2115+
h = (u16 *)(b + ori_offset);
2116+
*h = n * sizeof(handler);
2117+
local_flush_icache_range((unsigned long)b,
2118+
(unsigned long)(b+handler_len));
21482119

21492120
return (void *)old_handler;
21502121
}
21512122

2152-
void *set_vi_handler(int n, vi_handler_t addr)
2153-
{
2154-
return set_vi_srs_handler(n, addr, 0);
2155-
}
2156-
21572123
extern void tlb_init(void);
21582124

21592125
/*

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