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airliedairlied
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Merge tag 'amd-drm-fixes-5.18-2022-04-13' of https://gitlab.freedesktop.org/agd5f/linux into drm-fixes
amd-drm-fixes-5.18-2022-04-13: amdgpu: - Fix for alpha properly in pre-multiplied mode - Fix VCN 3.1.2 firmware name - Suspend/resume fix - Add a gfxoff quirk for Mac vega20 board - DCN 3.1.6 spread spectrum fix Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220414025821.5811-1-alexander.deucher@amd.com
2 parents 98a71d1 + aadaeca commit 8e401ff

8 files changed

Lines changed: 37 additions & 21 deletions

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‎drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c‎

Lines changed: 12 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -2323,18 +2323,23 @@ static int amdgpu_pmops_suspend(struct device *dev)
23232323
{
23242324
struct drm_device *drm_dev = dev_get_drvdata(dev);
23252325
struct amdgpu_device *adev = drm_to_adev(drm_dev);
2326-
int r;
23272326

23282327
if (amdgpu_acpi_is_s0ix_active(adev))
23292328
adev->in_s0ix = true;
23302329
else
23312330
adev->in_s3 = true;
2332-
r = amdgpu_device_suspend(drm_dev, true);
2333-
if (r)
2334-
return r;
2331+
return amdgpu_device_suspend(drm_dev, true);
2332+
}
2333+
2334+
static int amdgpu_pmops_suspend_noirq(struct device *dev)
2335+
{
2336+
struct drm_device *drm_dev = dev_get_drvdata(dev);
2337+
struct amdgpu_device *adev = drm_to_adev(drm_dev);
2338+
23352339
if (!adev->in_s0ix)
2336-
r = amdgpu_asic_reset(adev);
2337-
return r;
2340+
return amdgpu_asic_reset(adev);
2341+
2342+
return 0;
23382343
}
23392344

23402345
static int amdgpu_pmops_resume(struct device *dev)
@@ -2575,6 +2580,7 @@ static const struct dev_pm_ops amdgpu_pm_ops = {
25752580
.prepare = amdgpu_pmops_prepare,
25762581
.complete = amdgpu_pmops_complete,
25772582
.suspend = amdgpu_pmops_suspend,
2583+
.suspend_noirq = amdgpu_pmops_suspend_noirq,
25782584
.resume = amdgpu_pmops_resume,
25792585
.freeze = amdgpu_pmops_freeze,
25802586
.thaw = amdgpu_pmops_thaw,

‎drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -52,7 +52,7 @@
5252
#define FIRMWARE_ALDEBARAN "amdgpu/aldebaran_vcn.bin"
5353
#define FIRMWARE_BEIGE_GOBY "amdgpu/beige_goby_vcn.bin"
5454
#define FIRMWARE_YELLOW_CARP "amdgpu/yellow_carp_vcn.bin"
55-
#define FIRMWARE_VCN_3_1_2 "amdgpu/vcn_3_1_2_vcn.bin"
55+
#define FIRMWARE_VCN_3_1_2 "amdgpu/vcn_3_1_2.bin"
5656

5757
MODULE_FIRMWARE(FIRMWARE_RAVEN);
5858
MODULE_FIRMWARE(FIRMWARE_PICASSO);

‎drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1205,6 +1205,8 @@ static const struct amdgpu_gfxoff_quirk amdgpu_gfxoff_quirk_list[] = {
12051205
{ 0x1002, 0x15dd, 0x103c, 0x83e7, 0xd3 },
12061206
/* GFXOFF is unstable on C6 parts with a VBIOS 113-RAVEN-114 */
12071207
{ 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc6 },
1208+
/* Apple MacBook Pro (15-inch, 2019) Radeon Pro Vega 20 4 GB */
1209+
{ 0x1002, 0x69af, 0x106b, 0x019a, 0xc0 },
12081210
{ 0, 0, 0, 0, 0 },
12091211
};
12101212

‎drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -374,7 +374,7 @@ void dce_clock_read_ss_info(struct clk_mgr_internal *clk_mgr_dce)
374374
clk_mgr_dce->dprefclk_ss_percentage =
375375
info.spread_spectrum_percentage;
376376
}
377-
if (clk_mgr_dce->base.ctx->dc->debug.ignore_dpref_ss)
377+
if (clk_mgr_dce->base.ctx->dc->config.ignore_dpref_ss)
378378
clk_mgr_dce->dprefclk_ss_percentage = 0;
379379
}
380380
}

‎drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -686,8 +686,8 @@ void dcn316_clk_mgr_construct(
686686
clk_mgr->base.base.dprefclk_khz = dcn316_smu_get_dpref_clk(&clk_mgr->base);
687687
clk_mgr->base.dccg->ref_dtbclk_khz = clk_mgr->base.base.dprefclk_khz;
688688
dce_clock_read_ss_info(&clk_mgr->base);
689-
clk_mgr->base.dccg->ref_dtbclk_khz =
690-
dce_adjust_dp_ref_freq_for_ss(&clk_mgr->base, clk_mgr->base.base.dprefclk_khz);
689+
/*clk_mgr->base.dccg->ref_dtbclk_khz =
690+
dce_adjust_dp_ref_freq_for_ss(&clk_mgr->base, clk_mgr->base.base.dprefclk_khz);*/
691691

692692
clk_mgr->base.base.bw_params = &dcn316_bw_params;
693693

‎drivers/gpu/drm/amd/display/dc/dc.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -340,6 +340,7 @@ struct dc_config {
340340
bool is_asymmetric_memory;
341341
bool is_single_rank_dimm;
342342
bool use_pipe_ctx_sync_logic;
343+
bool ignore_dpref_ss;
343344
};
344345

345346
enum visual_confirm {
@@ -729,7 +730,6 @@ struct dc_debug_options {
729730
bool apply_vendor_specific_lttpr_wa;
730731
bool extended_blank_optimization;
731732
union aux_wake_wa_options aux_wake_wa;
732-
bool ignore_dpref_ss;
733733
uint8_t psr_power_use_phy_fsm;
734734
};
735735

‎drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c‎

Lines changed: 9 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -2522,14 +2522,18 @@ void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
25222522
struct mpc *mpc = dc->res_pool->mpc;
25232523
struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params);
25242524

2525-
if (per_pixel_alpha)
2526-
blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA;
2527-
else
2528-
blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA;
2529-
25302525
blnd_cfg.overlap_only = false;
25312526
blnd_cfg.global_gain = 0xff;
25322527

2528+
if (per_pixel_alpha && pipe_ctx->plane_state->global_alpha) {
2529+
blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN;
2530+
blnd_cfg.global_gain = pipe_ctx->plane_state->global_alpha_value;
2531+
} else if (per_pixel_alpha) {
2532+
blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA;
2533+
} else {
2534+
blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA;
2535+
}
2536+
25332537
if (pipe_ctx->plane_state->global_alpha)
25342538
blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value;
25352539
else

‎drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c‎

Lines changed: 9 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -2344,14 +2344,18 @@ void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
23442344
struct mpc *mpc = dc->res_pool->mpc;
23452345
struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params);
23462346

2347-
if (per_pixel_alpha)
2348-
blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA;
2349-
else
2350-
blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA;
2351-
23522347
blnd_cfg.overlap_only = false;
23532348
blnd_cfg.global_gain = 0xff;
23542349

2350+
if (per_pixel_alpha && pipe_ctx->plane_state->global_alpha) {
2351+
blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN;
2352+
blnd_cfg.global_gain = pipe_ctx->plane_state->global_alpha_value;
2353+
} else if (per_pixel_alpha) {
2354+
blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA;
2355+
} else {
2356+
blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA;
2357+
}
2358+
23552359
if (pipe_ctx->plane_state->global_alpha)
23562360
blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value;
23572361
else

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