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konradybcioGeorgi Djakov
konradybcio
authored and
Georgi Djakov
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interconnect: qcom: sm8250: Retire DEFINE_QBCM
The struct definition macros are hard to read and compare, expand them. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Bjorn Andersson <quic_bjorande@quicinc.com> Link: https://lore.kernel.org/r/20230811-topic-icc_retire_macrosd-v1-18-c03aaeffc769@linaro.org Signed-off-by: Georgi Djakov <djakov@kernel.org>
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Lines changed: 240 additions & 27 deletions

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‎drivers/interconnect/qcom/sm8250.c‎

Lines changed: 240 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -1395,33 +1395,246 @@ static struct qcom_icc_node qup2_core_slave = {
13951395
.buswidth = 4,
13961396
};
13971397

1398-
DEFINE_QBCM(bcm_acv, "ACV", false, &ebi);
1399-
DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi);
1400-
DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc);
1401-
DEFINE_QBCM(bcm_mm0, "MM0", true, &qns_mem_noc_hf);
1402-
DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto);
1403-
DEFINE_QBCM(bcm_mm1, "MM1", false, &qnm_camnoc_hf, &qxm_mdp0, &qxm_mdp1);
1404-
DEFINE_QBCM(bcm_sh2, "SH2", false, &alm_gpu_tcu, &alm_sys_tcu);
1405-
DEFINE_QBCM(bcm_mm2, "MM2", false, &qns_mem_noc_sf);
1406-
DEFINE_QBCM(bcm_qup0, "QUP0", false, &qup0_core_master, &qup1_core_master, &qup2_core_master);
1407-
DEFINE_QBCM(bcm_sh3, "SH3", false, &qnm_cmpnoc);
1408-
DEFINE_QBCM(bcm_mm3, "MM3", false, &qnm_camnoc_icp, &qnm_camnoc_sf, &qnm_video0, &qnm_video1, &qnm_video_cvp);
1409-
DEFINE_QBCM(bcm_sh4, "SH4", false, &chm_apps);
1410-
DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_gemnoc_sf);
1411-
DEFINE_QBCM(bcm_co0, "CO0", false, &qns_cdsp_mem_noc);
1412-
DEFINE_QBCM(bcm_cn0, "CN0", true, &qnm_snoc, &xm_qdss_dap, &qhs_a1_noc_cfg, &qhs_a2_noc_cfg, &qhs_ahb2phy0, &qhs_ahb2phy1, &qhs_aoss, &qhs_camera_cfg, &qhs_clk_ctl, &qhs_compute_dsp, &qhs_cpr_cx, &qhs_cpr_mmcx, &qhs_cpr_mx, &qhs_crypto0_cfg, &qhs_cx_rdpm, &qhs_dcc_cfg, &qhs_ddrss_cfg, &qhs_display_cfg, &qhs_gpuss_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_ipc_router, &qhs_lpass_cfg, &qhs_mnoc_cfg, &qhs_npu_cfg, &qhs_pcie0_cfg, &qhs_pcie1_cfg, &qhs_pcie_modem_cfg, &qhs_pdm, &qhs_pimem_cfg, &qhs_prng, &qhs_qdss_cfg, &qhs_qspi, &qhs_qup0, &qhs_qup1, &qhs_qup2, &qhs_sdc2, &qhs_sdc4, &qhs_snoc_cfg, &qhs_tcsr, &qhs_tlmm0, &qhs_tlmm1, &qhs_tlmm2, &qhs_tsif, &qhs_ufs_card_cfg, &qhs_ufs_mem_cfg, &qhs_usb3_0, &qhs_usb3_1, &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, &qns_cnoc_a2noc, &srvc_cnoc);
1413-
DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem);
1414-
DEFINE_QBCM(bcm_sn2, "SN2", false, &qns_gemnoc_gc);
1415-
DEFINE_QBCM(bcm_co2, "CO2", false, &qnm_npu);
1416-
DEFINE_QBCM(bcm_sn3, "SN3", false, &qxs_pimem);
1417-
DEFINE_QBCM(bcm_sn4, "SN4", false, &xs_qdss_stm);
1418-
DEFINE_QBCM(bcm_sn5, "SN5", false, &xs_pcie_modem);
1419-
DEFINE_QBCM(bcm_sn6, "SN6", false, &xs_pcie_0, &xs_pcie_1);
1420-
DEFINE_QBCM(bcm_sn7, "SN7", false, &qnm_aggre1_noc);
1421-
DEFINE_QBCM(bcm_sn8, "SN8", false, &qnm_aggre2_noc);
1422-
DEFINE_QBCM(bcm_sn9, "SN9", false, &qnm_gemnoc_pcie);
1423-
DEFINE_QBCM(bcm_sn11, "SN11", false, &qnm_gemnoc);
1424-
DEFINE_QBCM(bcm_sn12, "SN12", false, &qns_pcie_modem_mem_noc, &qns_pcie_mem_noc);
1398+
static struct qcom_icc_bcm bcm_acv = {
1399+
.name = "ACV",
1400+
.keepalive = false,
1401+
.num_nodes = 1,
1402+
.nodes = { &ebi },
1403+
};
1404+
1405+
static struct qcom_icc_bcm bcm_mc0 = {
1406+
.name = "MC0",
1407+
.keepalive = true,
1408+
.num_nodes = 1,
1409+
.nodes = { &ebi },
1410+
};
1411+
1412+
static struct qcom_icc_bcm bcm_sh0 = {
1413+
.name = "SH0",
1414+
.keepalive = true,
1415+
.num_nodes = 1,
1416+
.nodes = { &qns_llcc },
1417+
};
1418+
1419+
static struct qcom_icc_bcm bcm_mm0 = {
1420+
.name = "MM0",
1421+
.keepalive = true,
1422+
.num_nodes = 1,
1423+
.nodes = { &qns_mem_noc_hf },
1424+
};
1425+
1426+
static struct qcom_icc_bcm bcm_ce0 = {
1427+
.name = "CE0",
1428+
.keepalive = false,
1429+
.num_nodes = 1,
1430+
.nodes = { &qxm_crypto },
1431+
};
1432+
1433+
static struct qcom_icc_bcm bcm_mm1 = {
1434+
.name = "MM1",
1435+
.keepalive = false,
1436+
.num_nodes = 3,
1437+
.nodes = { &qnm_camnoc_hf, &qxm_mdp0, &qxm_mdp1 },
1438+
};
1439+
1440+
static struct qcom_icc_bcm bcm_sh2 = {
1441+
.name = "SH2",
1442+
.keepalive = false,
1443+
.num_nodes = 2,
1444+
.nodes = { &alm_gpu_tcu, &alm_sys_tcu },
1445+
};
1446+
1447+
static struct qcom_icc_bcm bcm_mm2 = {
1448+
.name = "MM2",
1449+
.keepalive = false,
1450+
.num_nodes = 1,
1451+
.nodes = { &qns_mem_noc_sf },
1452+
};
1453+
1454+
static struct qcom_icc_bcm bcm_qup0 = {
1455+
.name = "QUP0",
1456+
.keepalive = false,
1457+
.num_nodes = 3,
1458+
.nodes = { &qup0_core_master, &qup1_core_master, &qup2_core_master },
1459+
};
1460+
1461+
static struct qcom_icc_bcm bcm_sh3 = {
1462+
.name = "SH3",
1463+
.keepalive = false,
1464+
.num_nodes = 1,
1465+
.nodes = { &qnm_cmpnoc },
1466+
};
1467+
1468+
static struct qcom_icc_bcm bcm_mm3 = {
1469+
.name = "MM3",
1470+
.keepalive = false,
1471+
.num_nodes = 5,
1472+
.nodes = { &qnm_camnoc_icp, &qnm_camnoc_sf, &qnm_video0, &qnm_video1, &qnm_video_cvp },
1473+
};
1474+
1475+
static struct qcom_icc_bcm bcm_sh4 = {
1476+
.name = "SH4",
1477+
.keepalive = false,
1478+
.num_nodes = 1,
1479+
.nodes = { &chm_apps },
1480+
};
1481+
1482+
static struct qcom_icc_bcm bcm_sn0 = {
1483+
.name = "SN0",
1484+
.keepalive = true,
1485+
.num_nodes = 1,
1486+
.nodes = { &qns_gemnoc_sf },
1487+
};
1488+
1489+
static struct qcom_icc_bcm bcm_co0 = {
1490+
.name = "CO0",
1491+
.keepalive = false,
1492+
.num_nodes = 1,
1493+
.nodes = { &qns_cdsp_mem_noc },
1494+
};
1495+
1496+
static struct qcom_icc_bcm bcm_cn0 = {
1497+
.name = "CN0",
1498+
.keepalive = true,
1499+
.num_nodes = 52,
1500+
.nodes = { &qnm_snoc,
1501+
&xm_qdss_dap,
1502+
&qhs_a1_noc_cfg,
1503+
&qhs_a2_noc_cfg,
1504+
&qhs_ahb2phy0,
1505+
&qhs_ahb2phy1,
1506+
&qhs_aoss,
1507+
&qhs_camera_cfg,
1508+
&qhs_clk_ctl,
1509+
&qhs_compute_dsp,
1510+
&qhs_cpr_cx,
1511+
&qhs_cpr_mmcx,
1512+
&qhs_cpr_mx,
1513+
&qhs_crypto0_cfg,
1514+
&qhs_cx_rdpm,
1515+
&qhs_dcc_cfg,
1516+
&qhs_ddrss_cfg,
1517+
&qhs_display_cfg,
1518+
&qhs_gpuss_cfg,
1519+
&qhs_imem_cfg,
1520+
&qhs_ipa,
1521+
&qhs_ipc_router,
1522+
&qhs_lpass_cfg,
1523+
&qhs_mnoc_cfg,
1524+
&qhs_npu_cfg,
1525+
&qhs_pcie0_cfg,
1526+
&qhs_pcie1_cfg,
1527+
&qhs_pcie_modem_cfg,
1528+
&qhs_pdm,
1529+
&qhs_pimem_cfg,
1530+
&qhs_prng,
1531+
&qhs_qdss_cfg,
1532+
&qhs_qspi,
1533+
&qhs_qup0,
1534+
&qhs_qup1,
1535+
&qhs_qup2,
1536+
&qhs_sdc2,
1537+
&qhs_sdc4,
1538+
&qhs_snoc_cfg,
1539+
&qhs_tcsr,
1540+
&qhs_tlmm0,
1541+
&qhs_tlmm1,
1542+
&qhs_tlmm2,
1543+
&qhs_tsif,
1544+
&qhs_ufs_card_cfg,
1545+
&qhs_ufs_mem_cfg,
1546+
&qhs_usb3_0,
1547+
&qhs_usb3_1,
1548+
&qhs_venus_cfg,
1549+
&qhs_vsense_ctrl_cfg,
1550+
&qns_cnoc_a2noc,
1551+
&srvc_cnoc
1552+
},
1553+
};
1554+
1555+
static struct qcom_icc_bcm bcm_sn1 = {
1556+
.name = "SN1",
1557+
.keepalive = false,
1558+
.num_nodes = 1,
1559+
.nodes = { &qxs_imem },
1560+
};
1561+
1562+
static struct qcom_icc_bcm bcm_sn2 = {
1563+
.name = "SN2",
1564+
.keepalive = false,
1565+
.num_nodes = 1,
1566+
.nodes = { &qns_gemnoc_gc },
1567+
};
1568+
1569+
static struct qcom_icc_bcm bcm_co2 = {
1570+
.name = "CO2",
1571+
.keepalive = false,
1572+
.num_nodes = 1,
1573+
.nodes = { &qnm_npu },
1574+
};
1575+
1576+
static struct qcom_icc_bcm bcm_sn3 = {
1577+
.name = "SN3",
1578+
.keepalive = false,
1579+
.num_nodes = 1,
1580+
.nodes = { &qxs_pimem },
1581+
};
1582+
1583+
static struct qcom_icc_bcm bcm_sn4 = {
1584+
.name = "SN4",
1585+
.keepalive = false,
1586+
.num_nodes = 1,
1587+
.nodes = { &xs_qdss_stm },
1588+
};
1589+
1590+
static struct qcom_icc_bcm bcm_sn5 = {
1591+
.name = "SN5",
1592+
.keepalive = false,
1593+
.num_nodes = 1,
1594+
.nodes = { &xs_pcie_modem },
1595+
};
1596+
1597+
static struct qcom_icc_bcm bcm_sn6 = {
1598+
.name = "SN6",
1599+
.keepalive = false,
1600+
.num_nodes = 2,
1601+
.nodes = { &xs_pcie_0, &xs_pcie_1 },
1602+
};
1603+
1604+
static struct qcom_icc_bcm bcm_sn7 = {
1605+
.name = "SN7",
1606+
.keepalive = false,
1607+
.num_nodes = 1,
1608+
.nodes = { &qnm_aggre1_noc },
1609+
};
1610+
1611+
static struct qcom_icc_bcm bcm_sn8 = {
1612+
.name = "SN8",
1613+
.keepalive = false,
1614+
.num_nodes = 1,
1615+
.nodes = { &qnm_aggre2_noc },
1616+
};
1617+
1618+
static struct qcom_icc_bcm bcm_sn9 = {
1619+
.name = "SN9",
1620+
.keepalive = false,
1621+
.num_nodes = 1,
1622+
.nodes = { &qnm_gemnoc_pcie },
1623+
};
1624+
1625+
static struct qcom_icc_bcm bcm_sn11 = {
1626+
.name = "SN11",
1627+
.keepalive = false,
1628+
.num_nodes = 1,
1629+
.nodes = { &qnm_gemnoc },
1630+
};
1631+
1632+
static struct qcom_icc_bcm bcm_sn12 = {
1633+
.name = "SN12",
1634+
.keepalive = false,
1635+
.num_nodes = 2,
1636+
.nodes = { &qns_pcie_modem_mem_noc, &qns_pcie_mem_noc },
1637+
};
14251638

14261639
static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
14271640
&bcm_sn12,

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