@@ -374,85 +374,6 @@ static void clk_sama7g5_master_best_diff(struct clk_rate_request *req,
374374 }
375375}
376376
377- static int clk_master_pres_determine_rate (struct clk_hw * hw ,
378- struct clk_rate_request * req )
379- {
380- struct clk_master * master = to_clk_master (hw );
381- struct clk_rate_request req_parent = * req ;
382- const struct clk_master_characteristics * characteristics =
383- master -> characteristics ;
384- struct clk_hw * parent ;
385- long best_rate = LONG_MIN , best_diff = LONG_MIN ;
386- u32 pres ;
387- int i ;
388-
389- if (master -> chg_pid < 0 )
390- return - EOPNOTSUPP ;
391-
392- parent = clk_hw_get_parent_by_index (hw , master -> chg_pid );
393- if (!parent )
394- return - EOPNOTSUPP ;
395-
396- for (i = 0 ; i <= MASTER_PRES_MAX ; i ++ ) {
397- if (characteristics -> have_div3_pres && i == MASTER_PRES_MAX )
398- pres = 3 ;
399- else
400- pres = 1 << i ;
401-
402- req_parent .rate = req -> rate * pres ;
403- if (__clk_determine_rate (parent , & req_parent ))
404- continue ;
405-
406- clk_sama7g5_master_best_diff (req , parent , req_parent .rate ,
407- & best_diff , & best_rate , pres );
408- if (!best_diff )
409- break ;
410- }
411-
412- return 0 ;
413- }
414-
415- static int clk_master_pres_set_rate (struct clk_hw * hw , unsigned long rate ,
416- unsigned long parent_rate )
417- {
418- struct clk_master * master = to_clk_master (hw );
419- unsigned long flags ;
420- unsigned int pres , mckr , tmp ;
421- int ret ;
422-
423- pres = DIV_ROUND_CLOSEST (parent_rate , rate );
424- if (pres > MASTER_PRES_MAX )
425- return - EINVAL ;
426-
427- else if (pres == 3 )
428- pres = MASTER_PRES_MAX ;
429- else if (pres )
430- pres = ffs (pres ) - 1 ;
431-
432- spin_lock_irqsave (master -> lock , flags );
433- ret = regmap_read (master -> regmap , master -> layout -> offset , & mckr );
434- if (ret )
435- goto unlock ;
436-
437- mckr &= master -> layout -> mask ;
438- tmp = (mckr >> master -> layout -> pres_shift ) & MASTER_PRES_MASK ;
439- if (pres == tmp )
440- goto unlock ;
441-
442- mckr &= ~(MASTER_PRES_MASK << master -> layout -> pres_shift );
443- mckr |= (pres << master -> layout -> pres_shift );
444- ret = regmap_write (master -> regmap , master -> layout -> offset , mckr );
445- if (ret )
446- goto unlock ;
447-
448- while (!clk_master_ready (master ))
449- cpu_relax ();
450- unlock :
451- spin_unlock_irqrestore (master -> lock , flags );
452-
453- return ret ;
454- }
455-
456377static unsigned long clk_master_pres_recalc_rate (struct clk_hw * hw ,
457378 unsigned long parent_rate )
458379{
@@ -539,13 +460,6 @@ static void clk_master_pres_restore_context(struct clk_hw *hw)
539460 pr_warn ("MCKR PRES was not configured properly by firmware!\n" );
540461}
541462
542- static void clk_master_pres_restore_context_chg (struct clk_hw * hw )
543- {
544- struct clk_master * master = to_clk_master (hw );
545-
546- clk_master_pres_set_rate (hw , master -> pms .rate , master -> pms .parent_rate );
547- }
548-
549463static const struct clk_ops master_pres_ops = {
550464 .prepare = clk_master_prepare ,
551465 .is_prepared = clk_master_is_prepared ,
@@ -555,25 +469,13 @@ static const struct clk_ops master_pres_ops = {
555469 .restore_context = clk_master_pres_restore_context ,
556470};
557471
558- static const struct clk_ops master_pres_ops_chg = {
559- .prepare = clk_master_prepare ,
560- .is_prepared = clk_master_is_prepared ,
561- .determine_rate = clk_master_pres_determine_rate ,
562- .recalc_rate = clk_master_pres_recalc_rate ,
563- .get_parent = clk_master_pres_get_parent ,
564- .set_rate = clk_master_pres_set_rate ,
565- .save_context = clk_master_pres_save_context ,
566- .restore_context = clk_master_pres_restore_context_chg ,
567- };
568-
569472static struct clk_hw * __init
570473at91_clk_register_master_internal (struct regmap * regmap ,
571474 const char * name , int num_parents ,
572475 const char * * parent_names ,
573476 const struct clk_master_layout * layout ,
574477 const struct clk_master_characteristics * characteristics ,
575- const struct clk_ops * ops , spinlock_t * lock , u32 flags ,
576- int chg_pid )
478+ const struct clk_ops * ops , spinlock_t * lock , u32 flags )
577479{
578480 struct clk_master * master ;
579481 struct clk_init_data init ;
@@ -599,7 +501,6 @@ at91_clk_register_master_internal(struct regmap *regmap,
599501 master -> layout = layout ;
600502 master -> characteristics = characteristics ;
601503 master -> regmap = regmap ;
602- master -> chg_pid = chg_pid ;
603504 master -> lock = lock ;
604505
605506 if (ops == & master_div_ops_chg ) {
@@ -628,19 +529,13 @@ at91_clk_register_master_pres(struct regmap *regmap,
628529 const char * * parent_names ,
629530 const struct clk_master_layout * layout ,
630531 const struct clk_master_characteristics * characteristics ,
631- spinlock_t * lock , u32 flags , int chg_pid )
532+ spinlock_t * lock )
632533{
633- const struct clk_ops * ops ;
634-
635- if (flags & CLK_SET_RATE_GATE )
636- ops = & master_pres_ops ;
637- else
638- ops = & master_pres_ops_chg ;
639-
640534 return at91_clk_register_master_internal (regmap , name , num_parents ,
641535 parent_names , layout ,
642- characteristics , ops ,
643- lock , flags , chg_pid );
536+ characteristics ,
537+ & master_pres_ops ,
538+ lock , CLK_SET_RATE_GATE );
644539}
645540
646541struct clk_hw * __init
@@ -661,7 +556,7 @@ at91_clk_register_master_div(struct regmap *regmap,
661556 hw = at91_clk_register_master_internal (regmap , name , 1 ,
662557 & parent_name , layout ,
663558 characteristics , ops ,
664- lock , flags , - EINVAL );
559+ lock , flags );
665560
666561 if (!IS_ERR (hw ) && safe_div ) {
667562 master_div = to_clk_master (hw );
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