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PCI: Cache ACS Capabilities register
The ACS Capability register is read-only. Cache it to allow quirks to override it and to avoid re-reading it. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> [bhelgaas: commit log] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Tested-by: Naresh Kamboju <naresh.kamboju@linaro.org> Link: https://patch.msgid.link/20260102-pci_acs-v3-2-72280b94d288@oss.qualcomm.com
1 parent c41e2fb commit 8f05a5f

2 files changed

Lines changed: 15 additions & 10 deletions

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drivers/pci/pci.c

Lines changed: 14 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -893,7 +893,6 @@ static const char *disable_acs_redir_param;
893893
static const char *config_acs_param;
894894

895895
struct pci_acs {
896-
u16 cap;
897896
u16 ctrl;
898897
u16 fw_ctrl;
899898
};
@@ -996,20 +995,20 @@ static void __pci_config_acs(struct pci_dev *dev, struct pci_acs *caps,
996995
static void pci_std_enable_acs(struct pci_dev *dev, struct pci_acs *caps)
997996
{
998997
/* Source Validation */
999-
caps->ctrl |= (caps->cap & PCI_ACS_SV);
998+
caps->ctrl |= (dev->acs_capabilities & PCI_ACS_SV);
1000999

10011000
/* P2P Request Redirect */
1002-
caps->ctrl |= (caps->cap & PCI_ACS_RR);
1001+
caps->ctrl |= (dev->acs_capabilities & PCI_ACS_RR);
10031002

10041003
/* P2P Completion Redirect */
1005-
caps->ctrl |= (caps->cap & PCI_ACS_CR);
1004+
caps->ctrl |= (dev->acs_capabilities & PCI_ACS_CR);
10061005

10071006
/* Upstream Forwarding */
1008-
caps->ctrl |= (caps->cap & PCI_ACS_UF);
1007+
caps->ctrl |= (dev->acs_capabilities & PCI_ACS_UF);
10091008

10101009
/* Enable Translation Blocking for external devices and noats */
10111010
if (pci_ats_disabled() || dev->external_facing || dev->untrusted)
1012-
caps->ctrl |= (caps->cap & PCI_ACS_TB);
1011+
caps->ctrl |= (dev->acs_capabilities & PCI_ACS_TB);
10131012
}
10141013

10151014
/**
@@ -1032,7 +1031,6 @@ void pci_enable_acs(struct pci_dev *dev)
10321031
if (!pos)
10331032
return;
10341033

1035-
pci_read_config_word(dev, pos + PCI_ACS_CAP, &caps.cap);
10361034
pci_read_config_word(dev, pos + PCI_ACS_CTRL, &caps.ctrl);
10371035
caps.fw_ctrl = caps.ctrl;
10381036

@@ -3515,7 +3513,7 @@ void pci_configure_ari(struct pci_dev *dev)
35153513
static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags)
35163514
{
35173515
int pos;
3518-
u16 cap, ctrl;
3516+
u16 ctrl;
35193517

35203518
pos = pdev->acs_cap;
35213519
if (!pos)
@@ -3526,8 +3524,7 @@ static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags)
35263524
* or only required if controllable. Features missing from the
35273525
* capability field can therefore be assumed as hard-wired enabled.
35283526
*/
3529-
pci_read_config_word(pdev, pos + PCI_ACS_CAP, &cap);
3530-
acs_flags &= (cap | PCI_ACS_EC);
3527+
acs_flags &= (pdev->acs_capabilities | PCI_ACS_EC);
35313528

35323529
pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl);
35333530
return (ctrl & acs_flags) == acs_flags;
@@ -3648,7 +3645,14 @@ bool pci_acs_path_enabled(struct pci_dev *start,
36483645
*/
36493646
void pci_acs_init(struct pci_dev *dev)
36503647
{
3648+
int pos;
3649+
36513650
dev->acs_cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
3651+
pos = dev->acs_cap;
3652+
if (!pos)
3653+
return;
3654+
3655+
pci_read_config_word(dev, pos + PCI_ACS_CAP, &dev->acs_capabilities);
36523656
}
36533657

36543658
/**

include/linux/pci.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -558,6 +558,7 @@ struct pci_dev {
558558
struct pci_tsm *tsm; /* TSM operation state */
559559
#endif
560560
u16 acs_cap; /* ACS Capability offset */
561+
u16 acs_capabilities; /* ACS Capabilities */
561562
u8 supported_speeds; /* Supported Link Speeds Vector */
562563
phys_addr_t rom; /* Physical address if not from BAR */
563564
size_t romlen; /* Length if not from BAR */

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