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81 | 81 |
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82 | 82 | sram: memory@80000000 { |
83 | 83 | device_type = "memory"; |
| 84 | + reg = <0x80000000 0x400000>, /* sram0 4 MiB */ |
| 85 | + <0x80400000 0x200000>, /* sram1 2 MiB */ |
| 86 | + <0x80600000 0x200000>; /* aisram 2 MiB */ |
| 87 | + }; |
| 88 | + |
| 89 | + sram_controller: memory-controller { |
84 | 90 | compatible = "canaan,k210-sram"; |
85 | | - reg = <0x80000000 0x400000>, |
86 | | - <0x80400000 0x200000>, |
87 | | - <0x80600000 0x200000>; |
88 | | - reg-names = "sram0", "sram1", "aisram"; |
89 | 91 | clocks = <&sysclk K210_CLK_SRAM0>, |
90 | 92 | <&sysclk K210_CLK_SRAM1>, |
91 | 93 | <&sysclk K210_CLK_AI>; |
|
173 | 175 | #address-cells = <1>; |
174 | 176 | #size-cells = <1>; |
175 | 177 | compatible = "simple-pm-bus"; |
176 | | - ranges; |
| 178 | + ranges = <0x50200000 0x50200000 0x200000>; |
177 | 179 | clocks = <&sysclk K210_CLK_APB0>; |
178 | 180 |
|
179 | 181 | gpio1: gpio@50200000 { |
|
261 | 263 | }; |
262 | 264 |
|
263 | 265 | i2s0: i2s@50250000 { |
264 | | - compatible = "snps,designware-i2s"; |
| 266 | + compatible = "canaan,k210-i2s", "snps,designware-i2s"; |
265 | 267 | reg = <0x50250000 0x200>; |
266 | 268 | interrupts = <5>; |
267 | 269 | clocks = <&sysclk K210_CLK_I2S0>; |
|
270 | 272 | }; |
271 | 273 |
|
272 | 274 | i2s1: i2s@50260000 { |
273 | | - compatible = "snps,designware-i2s"; |
| 275 | + compatible = "canaan,k210-i2s", "snps,designware-i2s"; |
274 | 276 | reg = <0x50260000 0x200>; |
275 | 277 | interrupts = <6>; |
276 | 278 | clocks = <&sysclk K210_CLK_I2S1>; |
|
279 | 281 | }; |
280 | 282 |
|
281 | 283 | i2s2: i2s@50270000 { |
282 | | - compatible = "snps,designware-i2s"; |
| 284 | + compatible = "canaan,k210-i2s", "snps,designware-i2s"; |
283 | 285 | reg = <0x50270000 0x200>; |
284 | 286 | interrupts = <7>; |
285 | 287 | clocks = <&sysclk K210_CLK_I2S2>; |
|
329 | 331 |
|
330 | 332 | timer0: timer@502d0000 { |
331 | 333 | compatible = "snps,dw-apb-timer"; |
332 | | - reg = <0x502D0000 0x100>; |
333 | | - interrupts = <14>, <15>; |
| 334 | + reg = <0x502D0000 0x14>; |
| 335 | + interrupts = <14>; |
334 | 336 | clocks = <&sysclk K210_CLK_TIMER0>, |
335 | 337 | <&sysclk K210_CLK_APB0>; |
336 | 338 | clock-names = "timer", "pclk"; |
337 | 339 | resets = <&sysrst K210_RST_TIMER0>; |
338 | 340 | }; |
339 | 341 |
|
340 | | - timer1: timer@502e0000 { |
| 342 | + timer1: timer@502d0014 { |
| 343 | + compatible = "snps,dw-apb-timer"; |
| 344 | + reg = <0x502D0014 0x14>; |
| 345 | + interrupts = <15>; |
| 346 | + clocks = <&sysclk K210_CLK_TIMER0>, |
| 347 | + <&sysclk K210_CLK_APB0>; |
| 348 | + clock-names = "timer", "pclk"; |
| 349 | + resets = <&sysrst K210_RST_TIMER0>; |
| 350 | + }; |
| 351 | + |
| 352 | + timer2: timer@502e0000 { |
| 353 | + compatible = "snps,dw-apb-timer"; |
| 354 | + reg = <0x502E0000 0x14>; |
| 355 | + interrupts = <16>; |
| 356 | + clocks = <&sysclk K210_CLK_TIMER1>, |
| 357 | + <&sysclk K210_CLK_APB0>; |
| 358 | + clock-names = "timer", "pclk"; |
| 359 | + resets = <&sysrst K210_RST_TIMER1>; |
| 360 | + }; |
| 361 | + |
| 362 | + timer3: timer@502e0014 { |
341 | 363 | compatible = "snps,dw-apb-timer"; |
342 | | - reg = <0x502E0000 0x100>; |
343 | | - interrupts = <16>, <17>; |
| 364 | + reg = <0x502E0014 0x114>; |
| 365 | + interrupts = <17>; |
344 | 366 | clocks = <&sysclk K210_CLK_TIMER1>, |
345 | 367 | <&sysclk K210_CLK_APB0>; |
346 | 368 | clock-names = "timer", "pclk"; |
347 | 369 | resets = <&sysrst K210_RST_TIMER1>; |
348 | 370 | }; |
349 | 371 |
|
350 | | - timer2: timer@502f0000 { |
| 372 | + timer4: timer@502f0000 { |
351 | 373 | compatible = "snps,dw-apb-timer"; |
352 | | - reg = <0x502F0000 0x100>; |
353 | | - interrupts = <18>, <19>; |
| 374 | + reg = <0x502F0000 0x14>; |
| 375 | + interrupts = <18>; |
| 376 | + clocks = <&sysclk K210_CLK_TIMER2>, |
| 377 | + <&sysclk K210_CLK_APB0>; |
| 378 | + clock-names = "timer", "pclk"; |
| 379 | + resets = <&sysrst K210_RST_TIMER2>; |
| 380 | + }; |
| 381 | + |
| 382 | + timer5: timer@502f0014 { |
| 383 | + compatible = "snps,dw-apb-timer"; |
| 384 | + reg = <0x502F0014 0x14>; |
| 385 | + interrupts = <19>; |
354 | 386 | clocks = <&sysclk K210_CLK_TIMER2>, |
355 | 387 | <&sysclk K210_CLK_APB0>; |
356 | 388 | clock-names = "timer", "pclk"; |
|
362 | 394 | #address-cells = <1>; |
363 | 395 | #size-cells = <1>; |
364 | 396 | compatible = "simple-pm-bus"; |
365 | | - ranges; |
| 397 | + ranges = <0x50400000 0x50400000 0x40100>; |
366 | 398 | clocks = <&sysclk K210_CLK_APB1>; |
367 | 399 |
|
368 | 400 | wdt0: watchdog@50400000 { |
|
417 | 449 | #address-cells = <1>; |
418 | 450 | #size-cells = <1>; |
419 | 451 | compatible = "simple-pm-bus"; |
420 | | - ranges; |
| 452 | + ranges = <0x52000000 0x52000000 0x2000200>; |
421 | 453 | clocks = <&sysclk K210_CLK_APB2>; |
422 | 454 |
|
423 | 455 | spi0: spi@52000000 { |
|
431 | 463 | clock-names = "ssi_clk", "pclk"; |
432 | 464 | resets = <&sysrst K210_RST_SPI0>; |
433 | 465 | reset-names = "spi"; |
434 | | - spi-max-frequency = <25000000>; |
435 | 466 | num-cs = <4>; |
436 | 467 | reg-io-width = <4>; |
437 | 468 | }; |
|
447 | 478 | clock-names = "ssi_clk", "pclk"; |
448 | 479 | resets = <&sysrst K210_RST_SPI1>; |
449 | 480 | reset-names = "spi"; |
450 | | - spi-max-frequency = <25000000>; |
451 | 481 | num-cs = <4>; |
452 | 482 | reg-io-width = <4>; |
453 | 483 | }; |
|
463 | 493 | clock-names = "ssi_clk", "pclk"; |
464 | 494 | resets = <&sysrst K210_RST_SPI3>; |
465 | 495 | reset-names = "spi"; |
466 | | - /* Could possibly go up to 200 MHz */ |
467 | | - spi-max-frequency = <100000000>; |
| 496 | + |
468 | 497 | num-cs = <4>; |
469 | 498 | reg-io-width = <4>; |
470 | 499 | }; |
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