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arm64: dts: mediatek: mt8186: Wire up CPU frequency/voltage scaling
This adds clocks, dynamic power coefficients, and OPP tables for the CPU cores, so that everything required at the SoC level for CPU freqency and voltage scaling is available. Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230609072906.2784594-3-wenst@chromium.org Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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‎arch/arm64/boot/dts/mediatek/mt8186.dtsi‎

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@@ -120,6 +120,208 @@
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};
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};
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cluster0_opp: opp-table-cluster0 {
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compatible = "operating-points-v2";
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opp-shared;
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opp-500000000 {
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opp-hz = /bits/ 64 <500000000>;
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opp-microvolt = <600000>;
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required-opps = <&cci_opp_0>;
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};
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opp-774000000 {
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opp-hz = /bits/ 64 <774000000>;
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opp-microvolt = <675000>;
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required-opps = <&cci_opp_1>;
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};
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opp-875000000 {
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opp-hz = /bits/ 64 <875000000>;
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opp-microvolt = <700000>;
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required-opps = <&cci_opp_2>;
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};
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opp-975000000 {
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opp-hz = /bits/ 64 <975000000>;
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opp-microvolt = <725000>;
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required-opps = <&cci_opp_3>;
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};
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opp-1075000000 {
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opp-hz = /bits/ 64 <1075000000>;
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opp-microvolt = <750000>;
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required-opps = <&cci_opp_4>;
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};
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opp-1175000000 {
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opp-hz = /bits/ 64 <1175000000>;
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opp-microvolt = <775000>;
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required-opps = <&cci_opp_5>;
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};
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opp-1275000000 {
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opp-hz = /bits/ 64 <1275000000>;
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opp-microvolt = <800000>;
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required-opps = <&cci_opp_6>;
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};
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opp-1375000000 {
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opp-hz = /bits/ 64 <1375000000>;
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opp-microvolt = <825000>;
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required-opps = <&cci_opp_7>;
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};
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opp-1500000000 {
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opp-hz = /bits/ 64 <1500000000>;
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opp-microvolt = <856250>;
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required-opps = <&cci_opp_8>;
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};
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opp-1618000000 {
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opp-hz = /bits/ 64 <1618000000>;
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opp-microvolt = <875000>;
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required-opps = <&cci_opp_9>;
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};
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opp-1666000000 {
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opp-hz = /bits/ 64 <1666000000>;
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opp-microvolt = <900000>;
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required-opps = <&cci_opp_10>;
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};
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opp-1733000000 {
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opp-hz = /bits/ 64 <1733000000>;
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opp-microvolt = <925000>;
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required-opps = <&cci_opp_11>;
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};
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opp-1800000000 {
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opp-hz = /bits/ 64 <1800000000>;
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opp-microvolt = <950000>;
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required-opps = <&cci_opp_12>;
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};
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opp-1866000000 {
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opp-hz = /bits/ 64 <1866000000>;
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opp-microvolt = <981250>;
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required-opps = <&cci_opp_13>;
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};
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opp-1933000000 {
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opp-hz = /bits/ 64 <1933000000>;
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opp-microvolt = <1006250>;
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required-opps = <&cci_opp_14>;
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};
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opp-2000000000 {
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opp-hz = /bits/ 64 <2000000000>;
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opp-microvolt = <1031250>;
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required-opps = <&cci_opp_15>;
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};
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};
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cluster1_opp: opp-table-cluster1 {
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compatible = "operating-points-v2";
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opp-shared;
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opp-774000000 {
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opp-hz = /bits/ 64 <774000000>;
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opp-microvolt = <675000>;
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required-opps = <&cci_opp_0>;
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};
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opp-835000000 {
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opp-hz = /bits/ 64 <835000000>;
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opp-microvolt = <693750>;
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required-opps = <&cci_opp_1>;
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};
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opp-919000000 {
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opp-hz = /bits/ 64 <919000000>;
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opp-microvolt = <718750>;
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required-opps = <&cci_opp_2>;
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};
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opp-1002000000 {
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opp-hz = /bits/ 64 <1002000000>;
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opp-microvolt = <743750>;
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required-opps = <&cci_opp_3>;
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};
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opp-1085000000 {
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opp-hz = /bits/ 64 <1085000000>;
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opp-microvolt = <775000>;
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required-opps = <&cci_opp_4>;
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};
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opp-1169000000 {
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opp-hz = /bits/ 64 <1169000000>;
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opp-microvolt = <800000>;
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required-opps = <&cci_opp_5>;
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};
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opp-1308000000 {
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opp-hz = /bits/ 64 <1308000000>;
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opp-microvolt = <843750>;
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required-opps = <&cci_opp_6>;
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};
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opp-1419000000 {
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opp-hz = /bits/ 64 <1419000000>;
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opp-microvolt = <875000>;
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required-opps = <&cci_opp_7>;
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};
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opp-1530000000 {
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opp-hz = /bits/ 64 <1530000000>;
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opp-microvolt = <912500>;
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required-opps = <&cci_opp_8>;
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};
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opp-1670000000 {
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opp-hz = /bits/ 64 <1670000000>;
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opp-microvolt = <956250>;
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required-opps = <&cci_opp_9>;
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};
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opp-1733000000 {
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opp-hz = /bits/ 64 <1733000000>;
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opp-microvolt = <981250>;
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required-opps = <&cci_opp_10>;
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};
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opp-1796000000 {
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opp-hz = /bits/ 64 <1796000000>;
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opp-microvolt = <1012500>;
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required-opps = <&cci_opp_11>;
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};
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opp-1860000000 {
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opp-hz = /bits/ 64 <1860000000>;
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opp-microvolt = <1037500>;
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required-opps = <&cci_opp_12>;
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};
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opp-1923000000 {
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opp-hz = /bits/ 64 <1923000000>;
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opp-microvolt = <1062500>;
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required-opps = <&cci_opp_13>;
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};
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cluster1_opp_14: opp-1986000000 {
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opp-hz = /bits/ 64 <1986000000>;
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opp-microvolt = <1093750>;
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required-opps = <&cci_opp_14>;
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};
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cluster1_opp_15: opp-2050000000 {
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opp-hz = /bits/ 64 <2050000000>;
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opp-microvolt = <1118750>;
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required-opps = <&cci_opp_15>;
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};
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};
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123325
cpus {
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#address-cells = <1>;
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#size-cells = <0>;
@@ -166,6 +368,11 @@
166368
reg = <0x000>;
167369
enable-method = "psci";
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clock-frequency = <2000000000>;
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clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>,
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<&apmixedsys CLK_APMIXED_MAINPLL>;
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clock-names = "cpu", "intermediate";
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operating-points-v2 = <&cluster0_opp>;
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dynamic-power-coefficient = <84>;
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capacity-dmips-mhz = <382>;
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cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
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i-cache-size = <32768>;
@@ -185,6 +392,11 @@
185392
reg = <0x100>;
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enable-method = "psci";
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clock-frequency = <2000000000>;
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clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>,
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<&apmixedsys CLK_APMIXED_MAINPLL>;
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clock-names = "cpu", "intermediate";
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operating-points-v2 = <&cluster0_opp>;
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dynamic-power-coefficient = <84>;
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capacity-dmips-mhz = <382>;
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cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
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i-cache-size = <32768>;
@@ -204,6 +416,11 @@
204416
reg = <0x200>;
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enable-method = "psci";
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clock-frequency = <2000000000>;
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clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>,
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<&apmixedsys CLK_APMIXED_MAINPLL>;
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clock-names = "cpu", "intermediate";
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operating-points-v2 = <&cluster0_opp>;
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dynamic-power-coefficient = <84>;
207424
capacity-dmips-mhz = <382>;
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cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
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i-cache-size = <32768>;
@@ -223,6 +440,11 @@
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reg = <0x300>;
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enable-method = "psci";
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clock-frequency = <2000000000>;
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clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>,
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<&apmixedsys CLK_APMIXED_MAINPLL>;
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clock-names = "cpu", "intermediate";
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operating-points-v2 = <&cluster0_opp>;
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dynamic-power-coefficient = <84>;
226448
capacity-dmips-mhz = <382>;
227449
cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
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i-cache-size = <32768>;
@@ -242,6 +464,11 @@
242464
reg = <0x400>;
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enable-method = "psci";
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clock-frequency = <2000000000>;
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clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>,
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<&apmixedsys CLK_APMIXED_MAINPLL>;
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clock-names = "cpu", "intermediate";
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operating-points-v2 = <&cluster0_opp>;
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dynamic-power-coefficient = <84>;
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capacity-dmips-mhz = <382>;
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cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
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i-cache-size = <32768>;
@@ -261,6 +488,11 @@
261488
reg = <0x500>;
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enable-method = "psci";
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clock-frequency = <2000000000>;
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clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>,
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<&apmixedsys CLK_APMIXED_MAINPLL>;
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clock-names = "cpu", "intermediate";
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operating-points-v2 = <&cluster0_opp>;
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dynamic-power-coefficient = <84>;
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capacity-dmips-mhz = <382>;
265497
cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
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i-cache-size = <32768>;
@@ -280,6 +512,11 @@
280512
reg = <0x600>;
281513
enable-method = "psci";
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clock-frequency = <2050000000>;
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clocks = <&mcusys CLK_MCU_ARMPLL_BL_SEL>,
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<&apmixedsys CLK_APMIXED_MAINPLL>;
517+
clock-names = "cpu", "intermediate";
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operating-points-v2 = <&cluster1_opp>;
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dynamic-power-coefficient = <335>;
283520
capacity-dmips-mhz = <1024>;
284521
cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
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i-cache-size = <65536>;
@@ -299,6 +536,11 @@
299536
reg = <0x700>;
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enable-method = "psci";
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clock-frequency = <2050000000>;
539+
clocks = <&mcusys CLK_MCU_ARMPLL_BL_SEL>,
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<&apmixedsys CLK_APMIXED_MAINPLL>;
541+
clock-names = "cpu", "intermediate";
542+
operating-points-v2 = <&cluster1_opp>;
543+
dynamic-power-coefficient = <335>;
302544
capacity-dmips-mhz = <1024>;
303545
cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
304546
i-cache-size = <65536>;

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