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Merge tag 'amd-drm-next-6.5-2023-06-09' of https://gitlab.freedesktop.org/agd5f/linux into drm-next
amd-drm-next-6.5-2023-06-02: amdgpu: - SR-IOV fixes - Warning fixes - Misc code cleanups and spelling fixes - DCN 3.2 updates - Improved DC FAMS support for better power management - Improved DC SubVP support for better power management - DCN 3.1.x fixes - Max IB size query - DC GPU reset fixes - RAS updates - DCN 3.0.x fixes - S/G display fixes - CP shadow buffer support - Implement connector force callback - Z8 power improvements - PSP 13.0.10 vbflash support - Mode2 reset fixes - Store MQDs in VRAM to improve queue switch latency - VCN 3.x fixes - JPEG 3.x fixes - Enable DC_FP on LoongArch - GFXOFF fixes - GC 9.4.3 partition support - SDMA 4.4.2 partition support - VCN/JPEG 4.0.3 partition support - VCN 4.0.3 updates - NBIO 7.9 updates - GC 9.4.3 updates - Take NUMA into account when allocating memory - Handle NUMA for partitions - SMU 13.0.6 updates - GC 9.4.3 RAS updates - Stop including unused swiotlb.h - SMU 13.0.7 fixes - Fix clock output ordering on some APUs - Clean up DC FPGA code - GFX9 preemption fixes - Misc irq fixes - S0ix fixes - Add new DRM_AMDGPU_WERROR config parameter to help with CI - PCIe fix for RDNA2 - kdoc fixes - Documentation updates amdkfd: - Query TTM mem limit rather than hardcoding it - GC 9.4.3 partition support - Handle NUMA for partitions radeon: - Fix possible double free - Stop including unused swiotlb.h - Fix possible division by zero ttm: - Add query for TTM mem limit - Add NUMA awareness to pools - Export ttm_pool_fini() UAPI: - Add new ctx query flag to better handle GPU resets Mesa MR: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22290 - Add new interface to query and set shadow buffer for RDNA3 Mesa MR: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21986 - Add new INFO query for max IB size Proposed userspace: https://gitlab.freedesktop.org/bnieuwenhuizen/mesa/-/commits/ib-rejection-v3 amd-drm-next-6.5-2023-06-09: amdgpu: - S0ix fixes - Initial SMU13 Overdrive support - kdoc fixes - Misc clode cleanups - Flexible array fixes - Display OTG fixes - SMU 13.0.6 updates - Revert some broken clock counter updates - Misc display fixes - GFX9 preemption fixes - Add support for newer EEPROM bad page table format - Add missing radeon secondary id - Add support for new colorspace KMS API - CSA fix - Stable pstate fixes for APUs - make vbl interface admin only - Handle PCI accelerator class amdkfd: - Add debugger support for gdb radeon: - Fix possible UAF drm: - Add Colorspace functionality UAPI: - Add debugger interface for enabling gdb Proposed userspace: https://github.com/ROCm-Developer-Tools/ROCdbgapi/tree/wip-dbgapi - Add KMS colorspace API Discussion: https://lists.freedesktop.org/archives/dri-devel/2023-June/408128.html From: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230609174817.7764-1-alexander.deucher@amd.com
2 parents ba57b9b + 3b718dc commit 901bdf5

498 files changed

Lines changed: 45770 additions & 8019 deletions

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‎Documentation/gpu/amdgpu/apu-asic-info-table.csv‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5,6 +5,8 @@ Ryzen 4000 series, RENOIR, DCN 2.1, 9.3, VCN 2.2, 4.1.2, 11.0.3
55
Ryzen 3000 series / AMD Ryzen Embedded V1*/R1* with Radeon Vega Gfx, RAVEN2, DCN 1.0, 9.2.2, VCN 1.0.1, 4.1.1, 10.0.1
66
SteamDeck, VANGOGH, DCN 3.0.1, 10.3.1, VCN 3.1.0, 5.2.1, 11.5.0
77
Ryzen 5000 series / Ryzen 7x30 series, GREEN SARDINE / Cezanne / Barcelo / Barcelo-R, DCN 2.1, 9.3, VCN 2.2, 4.1.1, 12.0.1
8-
Ryzen 6000 series / Ryzen 7x35 series, YELLOW CARP / Rembrandt / Rembrandt+, 3.1.2, 10.3.3, VCN 3.1.1, 5.2.3, 13.0.3
8+
Ryzen 6000 series / Ryzen 7x35 series / Ryzen 7x36 series, YELLOW CARP / Rembrandt / Rembrandt-R, 3.1.2, 10.3.3, VCN 3.1.1, 5.2.3, 13.0.3
99
Ryzen 7000 series (AM5), Raphael, 3.1.5, 10.3.6, 3.1.2, 5.2.6, 13.0.5
10+
Ryzen 7x45 series (FL1), / Dragon Range, 3.1.5, 10.3.6, 3.1.2, 5.2.6, 13.0.5
1011
Ryzen 7x20 series, Mendocino, 3.1.6, 10.3.7, 3.1.1, 5.2.7, 13.0.8
12+
Ryzen 7x40 series, Phoenix, 3.1.4, 11.0.1 / 11.0.4, 4.0.2, 6.0.1, 13.0.4 / 13.0.11

‎drivers/gpu/drm/Makefile‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -140,6 +140,7 @@ obj-$(CONFIG_DRM_TTM) += ttm/
140140
obj-$(CONFIG_DRM_SCHED) += scheduler/
141141
obj-$(CONFIG_DRM_RADEON)+= radeon/
142142
obj-$(CONFIG_DRM_AMDGPU)+= amd/amdgpu/
143+
obj-$(CONFIG_DRM_AMDGPU)+= amd/amdxcp/
143144
obj-$(CONFIG_DRM_I915) += i915/
144145
obj-$(CONFIG_DRM_KMB_DISPLAY) += kmb/
145146
obj-$(CONFIG_DRM_MGAG200) += mgag200/

‎drivers/gpu/drm/amd/amdgpu/Kconfig‎

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -69,6 +69,16 @@ config DRM_AMDGPU_USERPTR
6969
This option selects CONFIG_HMM and CONFIG_HMM_MIRROR if it
7070
isn't already selected to enabled full userptr support.
7171

72+
config DRM_AMDGPU_WERROR
73+
bool "Force the compiler to throw an error instead of a warning when compiling"
74+
depends on DRM_AMDGPU
75+
depends on EXPERT
76+
depends on !COMPILE_TEST
77+
default n
78+
help
79+
Add -Werror to the build flags for amdgpu.ko.
80+
Only enable this if you are warning code for amdgpu.ko.
81+
7282
source "drivers/gpu/drm/amd/acp/Kconfig"
7383
source "drivers/gpu/drm/amd/display/Kconfig"
7484
source "drivers/gpu/drm/amd/amdkfd/Kconfig"

‎drivers/gpu/drm/amd/amdgpu/Makefile‎

Lines changed: 16 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -39,6 +39,15 @@ ccflags-y := -I$(FULL_AMD_PATH)/include/asic_reg \
3939
-I$(FULL_AMD_DISPLAY_PATH)/amdgpu_dm \
4040
-I$(FULL_AMD_PATH)/amdkfd
4141

42+
subdir-ccflags-y := -Wextra
43+
subdir-ccflags-y += $(call cc-option, -Wunused-but-set-variable)
44+
subdir-ccflags-y += -Wno-unused-parameter
45+
subdir-ccflags-y += -Wno-type-limits
46+
subdir-ccflags-y += -Wno-sign-compare
47+
subdir-ccflags-y += -Wno-missing-field-initializers
48+
subdir-ccflags-y += -Wno-override-init
49+
subdir-ccflags-$(CONFIG_DRM_AMDGPU_WERROR) += -Werror
50+
4251
amdgpu-y := amdgpu_drv.o
4352

4453
# add KMS driver
@@ -60,7 +69,7 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \
6069
amdgpu_umc.o smu_v11_0_i2c.o amdgpu_fru_eeprom.o amdgpu_rap.o \
6170
amdgpu_fw_attestation.o amdgpu_securedisplay.o \
6271
amdgpu_eeprom.o amdgpu_mca.o amdgpu_psp_ta.o amdgpu_lsdma.o \
63-
amdgpu_ring_mux.o
72+
amdgpu_ring_mux.o amdgpu_xcp.o
6473

6574
amdgpu-$(CONFIG_PROC_FS) += amdgpu_fdinfo.o
6675

@@ -78,7 +87,7 @@ amdgpu-y += \
7887
vega20_reg_init.o nbio_v7_4.o nbio_v2_3.o nv.o arct_reg_init.o mxgpu_nv.o \
7988
nbio_v7_2.o hdp_v4_0.o hdp_v5_0.o aldebaran_reg_init.o aldebaran.o soc21.o \
8089
sienna_cichlid.o smu_v13_0_10.o nbio_v4_3.o hdp_v6_0.o nbio_v7_7.o hdp_v5_2.o lsdma_v6_0.o \
81-
nbio_v7_9.o
90+
nbio_v7_9.o aqua_vanjaram_reg_init.o
8291

8392
# add DF block
8493
amdgpu-y += \
@@ -183,12 +192,14 @@ amdgpu-y += \
183192
vcn_v2_5.o \
184193
vcn_v3_0.o \
185194
vcn_v4_0.o \
195+
vcn_v4_0_3.o \
186196
amdgpu_jpeg.o \
187197
jpeg_v1_0.o \
188198
jpeg_v2_0.o \
189199
jpeg_v2_5.o \
190200
jpeg_v3_0.o \
191-
jpeg_v4_0.o
201+
jpeg_v4_0.o \
202+
jpeg_v4_0_3.o
192203

193204
# add ATHUB block
194205
amdgpu-y += \
@@ -203,6 +214,7 @@ amdgpu-y += \
203214
smuio_v11_0.o \
204215
smuio_v11_0_6.o \
205216
smuio_v13_0.o \
217+
smuio_v13_0_3.o \
206218
smuio_v13_0_6.o
207219

208220
# add reset block
@@ -228,6 +240,7 @@ amdgpu-y += \
228240
amdgpu_amdkfd_gfx_v9.o \
229241
amdgpu_amdkfd_arcturus.o \
230242
amdgpu_amdkfd_aldebaran.o \
243+
amdgpu_amdkfd_gc_9_4_3.o \
231244
amdgpu_amdkfd_gfx_v10.o \
232245
amdgpu_amdkfd_gfx_v10_3.o \
233246
amdgpu_amdkfd_gfx_v11.o

‎drivers/gpu/drm/amd/amdgpu/amdgpu.h‎

Lines changed: 74 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -107,8 +107,9 @@
107107
#include "amdgpu_fdinfo.h"
108108
#include "amdgpu_mca.h"
109109
#include "amdgpu_ras.h"
110+
#include "amdgpu_xcp.h"
110111

111-
#define MAX_GPU_INSTANCE 16
112+
#define MAX_GPU_INSTANCE 64
112113

113114
struct amdgpu_gpu_instance
114115
{
@@ -212,6 +213,8 @@ extern int amdgpu_noretry;
212213
extern int amdgpu_force_asic_type;
213214
extern int amdgpu_smartshift_bias;
214215
extern int amdgpu_use_xgmi_p2p;
216+
extern int amdgpu_mtype_local;
217+
extern bool enforce_isolation;
215218
#ifdef CONFIG_HSA_AMD
216219
extern int sched_policy;
217220
extern bool debug_evictions;
@@ -242,9 +245,10 @@ extern int amdgpu_num_kcq;
242245
extern int amdgpu_vcnfw_log;
243246
extern int amdgpu_sg_display;
244247

248+
extern int amdgpu_user_partt_mode;
249+
245250
#define AMDGPU_VM_MAX_NUM_CTX 4096
246251
#define AMDGPU_SG_THRESHOLD (256*1024*1024)
247-
#define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */
248252
#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
249253
#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
250254
#define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
@@ -282,6 +286,7 @@ extern int amdgpu_sg_display;
282286
#define AMDGPU_SMARTSHIFT_MAX_BIAS (100)
283287
#define AMDGPU_SMARTSHIFT_MIN_BIAS (-100)
284288

289+
struct amdgpu_xcp_mgr;
285290
struct amdgpu_device;
286291
struct amdgpu_irq_src;
287292
struct amdgpu_fpriv;
@@ -463,6 +468,8 @@ struct amdgpu_fpriv {
463468
struct mutex bo_list_lock;
464469
struct idr bo_list_handles;
465470
struct amdgpu_ctx_mgr ctx_mgr;
471+
/** GPU partition selection */
472+
uint32_t xcp_id;
466473
};
467474

468475
int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv);
@@ -573,6 +580,8 @@ struct amdgpu_asic_funcs {
573580
/* query video codecs */
574581
int (*query_video_codecs)(struct amdgpu_device *adev, bool encode,
575582
const struct amdgpu_video_codecs **codecs);
583+
/* encode "> 32bits" smn addressing */
584+
u64 (*encode_ext_smn_addressing)(int ext_id);
576585
};
577586

578587
/*
@@ -607,6 +616,9 @@ void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
607616
typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
608617
typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
609618

619+
typedef uint32_t (*amdgpu_rreg_ext_t)(struct amdgpu_device*, uint64_t);
620+
typedef void (*amdgpu_wreg_ext_t)(struct amdgpu_device*, uint64_t, uint32_t);
621+
610622
typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t);
611623
typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t);
612624

@@ -657,14 +669,25 @@ enum amd_hw_ip_block_type {
657669
MAX_HWIP
658670
};
659671

660-
#define HWIP_MAX_INSTANCE 28
672+
#define HWIP_MAX_INSTANCE 44
661673

662674
#define HW_ID_MAX 300
663675
#define IP_VERSION(mj, mn, rv) (((mj) << 16) | ((mn) << 8) | (rv))
664676
#define IP_VERSION_MAJ(ver) ((ver) >> 16)
665677
#define IP_VERSION_MIN(ver) (((ver) >> 8) & 0xFF)
666678
#define IP_VERSION_REV(ver) ((ver) & 0xFF)
667679

680+
struct amdgpu_ip_map_info {
681+
/* Map of logical to actual dev instances/mask */
682+
uint32_t dev_inst[MAX_HWIP][HWIP_MAX_INSTANCE];
683+
int8_t (*logical_to_dev_inst)(struct amdgpu_device *adev,
684+
enum amd_hw_ip_block_type block,
685+
int8_t inst);
686+
uint32_t (*logical_to_dev_mask)(struct amdgpu_device *adev,
687+
enum amd_hw_ip_block_type block,
688+
uint32_t mask);
689+
};
690+
668691
struct amd_powerplay {
669692
void *pp_handle;
670693
const struct amd_pm_funcs *pp_funcs;
@@ -750,6 +773,7 @@ struct amdgpu_device {
750773
struct amdgpu_acp acp;
751774
#endif
752775
struct amdgpu_hive_info *hive;
776+
struct amdgpu_xcp_mgr *xcp_mgr;
753777
/* ASIC */
754778
enum amd_asic_type asic_type;
755779
uint32_t family;
@@ -797,6 +821,8 @@ struct amdgpu_device {
797821
amdgpu_wreg_t pcie_wreg;
798822
amdgpu_rreg_t pciep_rreg;
799823
amdgpu_wreg_t pciep_wreg;
824+
amdgpu_rreg_ext_t pcie_rreg_ext;
825+
amdgpu_wreg_ext_t pcie_wreg_ext;
800826
amdgpu_rreg64_t pcie_rreg64;
801827
amdgpu_wreg64_t pcie_wreg64;
802828
/* protects concurrent UVD register access */
@@ -830,7 +856,7 @@ struct amdgpu_device {
830856
dma_addr_t dummy_page_addr;
831857
struct amdgpu_vm_manager vm_manager;
832858
struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS];
833-
unsigned num_vmhubs;
859+
DECLARE_BITMAP(vmhubs_mask, AMDGPU_MAX_VMHUBS);
834860

835861
/* memory management */
836862
struct amdgpu_mman mman;
@@ -962,6 +988,7 @@ struct amdgpu_device {
962988

963989
/* soc15 register offset based on ip, instance and segment */
964990
uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
991+
struct amdgpu_ip_map_info ip_map;
965992

966993
/* delayed work_func for deferring clockgating during resume */
967994
struct delayed_work delayed_init_work;
@@ -1020,6 +1047,9 @@ struct amdgpu_device {
10201047
struct pci_saved_state *pci_state;
10211048
pci_channel_state_t pci_channel_state;
10221049

1050+
/* Track auto wait count on s_barrier settings */
1051+
bool barrier_has_auto_waitcnt;
1052+
10231053
struct amdgpu_reset_control *reset_cntl;
10241054
uint32_t ip_versions[MAX_HWIP][HWIP_MAX_INSTANCE];
10251055

@@ -1050,6 +1080,8 @@ struct amdgpu_device {
10501080

10511081
bool job_hang;
10521082
bool dc_enabled;
1083+
/* Mask of active clusters */
1084+
uint32_t aid_mask;
10531085
};
10541086

10551087
static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev)
@@ -1081,11 +1113,18 @@ size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos,
10811113

10821114
void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
10831115
void *buf, size_t size, bool write);
1116+
uint32_t amdgpu_device_wait_on_rreg(struct amdgpu_device *adev,
1117+
uint32_t inst, uint32_t reg_addr, char reg_name[],
1118+
uint32_t expected_value, uint32_t mask);
10841119
uint32_t amdgpu_device_rreg(struct amdgpu_device *adev,
10851120
uint32_t reg, uint32_t acc_flags);
1121+
u32 amdgpu_device_indirect_rreg_ext(struct amdgpu_device *adev,
1122+
u64 reg_addr);
10861123
void amdgpu_device_wreg(struct amdgpu_device *adev,
10871124
uint32_t reg, uint32_t v,
10881125
uint32_t acc_flags);
1126+
void amdgpu_device_indirect_wreg_ext(struct amdgpu_device *adev,
1127+
u64 reg_addr, u32 reg_data);
10891128
void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev,
10901129
uint32_t reg, uint32_t v);
10911130
void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value);
@@ -1137,6 +1176,8 @@ int emu_soc_asic_init(struct amdgpu_device *adev);
11371176
#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
11381177
#define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
11391178
#define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
1179+
#define RREG32_PCIE_EXT(reg) adev->pcie_rreg_ext(adev, (reg))
1180+
#define WREG32_PCIE_EXT(reg, v) adev->pcie_wreg_ext(adev, (reg), (v))
11401181
#define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg))
11411182
#define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v))
11421183
#define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
@@ -1204,7 +1245,8 @@ int emu_soc_asic_init(struct amdgpu_device *adev);
12041245
/*
12051246
* ASICs macro.
12061247
*/
1207-
#define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
1248+
#define amdgpu_asic_set_vga_state(adev, state) \
1249+
((adev)->asic_funcs->set_vga_state ? (adev)->asic_funcs->set_vga_state((adev), (state)) : 0)
12081250
#define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
12091251
#define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev))
12101252
#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
@@ -1235,6 +1277,10 @@ int emu_soc_asic_init(struct amdgpu_device *adev);
12351277

12361278
#define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter));
12371279

1280+
#define for_each_inst(i, inst_mask) \
1281+
for (i = ffs(inst_mask) - 1; inst_mask; \
1282+
inst_mask &= ~(1U << i), i = ffs(inst_mask) - 1)
1283+
12381284
#define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
12391285

12401286
/* Common functions */
@@ -1348,6 +1394,12 @@ struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
13481394

13491395
/* amdgpu_acpi.c */
13501396

1397+
struct amdgpu_numa_info {
1398+
uint64_t size;
1399+
int pxm;
1400+
int nid;
1401+
};
1402+
13511403
/* ATCS Device/Driver State */
13521404
#define AMDGPU_ATCS_PSC_DEV_STATE_D0 0
13531405
#define AMDGPU_ATCS_PSC_DEV_STATE_D3_HOT 3
@@ -1365,15 +1417,32 @@ int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev,
13651417
u8 dev_state, bool drv_state);
13661418
int amdgpu_acpi_smart_shift_update(struct drm_device *dev, enum amdgpu_ss ss_state);
13671419
int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
1420+
int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, u64 *tmr_offset,
1421+
u64 *tmr_size);
1422+
int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, int xcc_id,
1423+
struct amdgpu_numa_info *numa_info);
13681424

13691425
void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps);
13701426
bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev);
13711427
void amdgpu_acpi_detect(void);
1428+
void amdgpu_acpi_release(void);
13721429
#else
13731430
static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
1431+
static inline int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev,
1432+
u64 *tmr_offset, u64 *tmr_size)
1433+
{
1434+
return -EINVAL;
1435+
}
1436+
static inline int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev,
1437+
int xcc_id,
1438+
struct amdgpu_numa_info *numa_info)
1439+
{
1440+
return -EINVAL;
1441+
}
13741442
static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
13751443
static inline bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) { return false; }
13761444
static inline void amdgpu_acpi_detect(void) { }
1445+
static inline void amdgpu_acpi_release(void) { }
13771446
static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; }
13781447
static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev,
13791448
u8 dev_state, bool drv_state) { return 0; }

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