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Merge patch series "Add basic ACPI support for RISC-V"
Sunil V L <sunilvl@ventanamicro.com> says: This patch series enables the basic ACPI infrastructure for RISC-V. Supporting external interrupt controllers is in progress and hence it is tested using poll based HVC SBI console and RAM disk. The first patch in this series is one of the patch from Jisheng's series [1] which is not merged yet. This patch is required to support ACPI since efi_init() which gets called before sbi_init() can enable static branches and hits a panic. Below are two ECRs approved by ASWG. RINTC - https://drive.google.com/file/d/1R6k4MshhN3WTT-hwqAquu5nX6xSEqK2l/view RHCT - https://drive.google.com/file/d/1nP3nFiH4jkPMp6COOxP6123DCZKR-tia/view Testing: 1) Build latest Qemu 2) Build EDK2 as per instructions in https://github.com/vlsunil/riscv-uefi-edk2-docs/wiki/RISC-V-Qemu-Virt-support 3) Build Linux after enabling SBI HVC and SBI earlycon CONFIG_RISCV_SBI_V01=y CONFIG_SERIAL_EARLYCON_RISCV_SBI=y CONFIG_HVC_RISCV_SBI=y 4) Build buildroot. Run with below command. qemu-system-riscv64 -nographic \ -drive file=Build/RiscVVirtQemu/RELEASE_GCC5/FV/RISCV_VIRT.fd,if=pflash,format=raw,unit=1 \ -machine virt -smp 16 -m 2G \ -kernel arch/riscv/boot/Image \ -initrd buildroot/output/images/rootfs.cpio \ -append "root=/dev/ram ro console=hvc0 earlycon=sbi" * b4-shazam-merge: RISC-V: Enable ACPI in defconfig RISC-V: time.c: Add ACPI support for time_init() clocksource/timer-riscv: Add ACPI support clocksource/timer-riscv: Refactor riscv_timer_init_dt() irqchip/riscv-intc: Add ACPI support RISC-V: cpu: Enable cpuinfo for ACPI systems RISC-V: cpufeature: Add ACPI support in riscv_fill_hwcap() RISC-V: only iterate over possible CPUs in ISA string parser RISC-V: smpboot: Add ACPI support in setup_smp() RISC-V: smpboot: Create wrapper setup_smp() drivers/acpi: RISC-V: Add RHCT related code RISC-V: ACPI: Cache and retrieve the RINTC structure RISC-V: Add ACPI initialization in setup_arch() ACPI: processor_core: RISC-V: Enable mapping processor to the hartid RISC-V: Add support to build the ACPI core ACPI: OSL: Make should_use_kmap() 0 for RISC-V ACPI: tables: Print RINTC information when MADT is parsed crypto: hisilicon/qm: Fix to enable build with RISC-V clang platform/surface: Disable for RISC-V riscv: move sbi_init() earlier before jump_label_init() Link: https://lore.kernel.org/r/20230515054928.2079268-1-sunilvl@ventanamicro.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2 parents ac9a786 + cc9e654 commit 90502d5

24 files changed

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‎Documentation/admin-guide/kernel-parameters.txt‎

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@@ -1,17 +1,17 @@
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acpi= [HW,ACPI,X86,ARM64]
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acpi= [HW,ACPI,X86,ARM64,RISCV64]
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Advanced Configuration and Power Interface
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Format: { force | on | off | strict | noirq | rsdt |
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copy_dsdt }
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force -- enable ACPI if default was off
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on -- enable ACPI but allow fallback to DT [arm64]
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on -- enable ACPI but allow fallback to DT [arm64,riscv64]
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off -- disable ACPI if default was on
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noirq -- do not use ACPI for IRQ routing
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strict -- Be less tolerant of platforms that are not
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strictly ACPI specification compliant.
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rsdt -- prefer RSDT over (default) XSDT
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copy_dsdt -- copy DSDT to memory
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For ARM64, ONLY "acpi=off", "acpi=on" or "acpi=force"
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are available
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For ARM64 and RISCV64, ONLY "acpi=off", "acpi=on" or
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"acpi=force" are available
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See also Documentation/power/runtime_pm.rst, pci=noacpi
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‎MAINTAINERS‎

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@@ -412,6 +412,13 @@ L: platform-driver-x86@vger.kernel.org
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S: Maintained
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F: drivers/platform/x86/serial-multi-instantiate.c
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ACPI FOR RISC-V (ACPI/riscv)
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M: Sunil V L <sunilvl@ventanamicro.com>
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L: linux-acpi@vger.kernel.org
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L: linux-riscv@lists.infradead.org
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S: Maintained
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F: drivers/acpi/riscv/
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ACPI PCC(Platform Communication Channel) MAILBOX DRIVER
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M: Sudeep Holla <sudeep.holla@arm.com>
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L: linux-acpi@vger.kernel.org

‎arch/riscv/Kconfig‎

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@@ -12,6 +12,8 @@ config 32BIT
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config RISCV
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def_bool y
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select ACPI_GENERIC_GSI if ACPI
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select ACPI_REDUCED_HARDWARE_ONLY if ACPI
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select ARCH_DMA_DEFAULT_COHERENT
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select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION
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select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2
@@ -707,6 +709,7 @@ config EFI
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depends on OF && !XIP_KERNEL
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depends on MMU
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default y
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select ARCH_SUPPORTS_ACPI if 64BIT
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select EFI_GENERIC_STUB
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select EFI_PARAMS_FROM_FDT
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select EFI_RUNTIME_WRAPPERS
@@ -816,3 +819,5 @@ source "drivers/cpufreq/Kconfig"
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endmenu # "CPU Power Management"
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source "arch/riscv/kvm/Kconfig"
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source "drivers/acpi/Kconfig"

‎arch/riscv/configs/defconfig‎

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@@ -37,6 +37,7 @@ CONFIG_PM=y
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CONFIG_CPU_IDLE=y
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CONFIG_VIRTUALIZATION=y
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CONFIG_KVM=m
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CONFIG_ACPI=y
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CONFIG_JUMP_LABEL=y
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CONFIG_MODULES=y
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CONFIG_MODULE_UNLOAD=y

‎arch/riscv/include/asm/acenv.h‎

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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* RISC-V specific ACPICA environments and implementation
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*/
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#ifndef _ASM_ACENV_H
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#define _ASM_ACENV_H
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/* This header is required unconditionally by the ACPI core */
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#endif /* _ASM_ACENV_H */

‎arch/riscv/include/asm/acpi.h‎

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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2013-2014, Linaro Ltd.
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* Author: Al Stone <al.stone@linaro.org>
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* Author: Graeme Gregory <graeme.gregory@linaro.org>
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* Author: Hanjun Guo <hanjun.guo@linaro.org>
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*
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* Copyright (C) 2021-2023, Ventana Micro Systems Inc.
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* Author: Sunil V L <sunilvl@ventanamicro.com>
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*/
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#ifndef _ASM_ACPI_H
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#define _ASM_ACPI_H
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/* Basic configuration for ACPI */
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#ifdef CONFIG_ACPI
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typedef u64 phys_cpuid_t;
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#define PHYS_CPUID_INVALID INVALID_HARTID
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/* ACPI table mapping after acpi_permanent_mmap is set */
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void *acpi_os_ioremap(acpi_physical_address phys, acpi_size size);
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#define acpi_os_ioremap acpi_os_ioremap
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#define acpi_strict 1 /* No out-of-spec workarounds on RISC-V */
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extern int acpi_disabled;
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extern int acpi_noirq;
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extern int acpi_pci_disabled;
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static inline void disable_acpi(void)
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{
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acpi_disabled = 1;
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acpi_pci_disabled = 1;
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acpi_noirq = 1;
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}
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static inline void enable_acpi(void)
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{
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acpi_disabled = 0;
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acpi_pci_disabled = 0;
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acpi_noirq = 0;
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}
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/*
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* The ACPI processor driver for ACPI core code needs this macro
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* to find out whether this cpu was already mapped (mapping from CPU hardware
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* ID to CPU logical ID) or not.
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*/
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#define cpu_physical_id(cpu) cpuid_to_hartid_map(cpu)
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/*
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* Since MADT must provide at least one RINTC structure, the
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* CPU will be always available in MADT on RISC-V.
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*/
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static inline bool acpi_has_cpu_in_madt(void)
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{
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return true;
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}
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static inline void arch_fix_phys_package_id(int num, u32 slot) { }
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void acpi_init_rintc_map(void);
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struct acpi_madt_rintc *acpi_cpu_get_madt_rintc(int cpu);
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u32 get_acpi_id_for_cpu(int cpu);
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int acpi_get_riscv_isa(struct acpi_table_header *table,
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unsigned int cpu, const char **isa);
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static inline int acpi_numa_get_nid(unsigned int cpu) { return NUMA_NO_NODE; }
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#else
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static inline void acpi_init_rintc_map(void) { }
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static inline struct acpi_madt_rintc *acpi_cpu_get_madt_rintc(int cpu)
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{
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return NULL;
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}
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static inline int acpi_get_riscv_isa(struct acpi_table_header *table,
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unsigned int cpu, const char **isa)
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{
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return -EINVAL;
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}
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#endif /* CONFIG_ACPI */
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#endif /*_ASM_ACPI_H*/

‎arch/riscv/include/asm/cpu.h‎

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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef _ASM_CPU_H
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#define _ASM_CPU_H
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/* This header is required unconditionally by the ACPI core */
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#endif /* _ASM_CPU_H */

‎arch/riscv/kernel/Makefile‎

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@@ -92,3 +92,4 @@ obj-$(CONFIG_COMPAT) += compat_signal.o
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obj-$(CONFIG_COMPAT) += compat_vdso/
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obj-$(CONFIG_64BIT) += pi/
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obj-$(CONFIG_ACPI) += acpi.o

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