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clocksource/drivers/timer-ti-dm: Simplify register reads with dmtimer_read()
We can simplify register read access by checking for the register write posted mode in the read function. This way we can combine the functions for __omap_dm_timer_read() and omap_dm_timer_read_reg() into a single function dmtimer_read(). We update the shared register access first, the timer revision specific register access will be updated in a later patch. Signed-off-by: Tony Lindgren <tony@atomide.com> Reviewed-by: Janusz Krzysztofik <jmkrzyszt@gmail.com> Link: https://lore.kernel.org/r/20220815131250.34603-3-tony@atomide.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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1 file changed

Lines changed: 40 additions & 48 deletions

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‎drivers/clocksource/timer-ti-dm.c‎

Lines changed: 40 additions & 48 deletions
Original file line numberDiff line numberDiff line change
@@ -44,14 +44,28 @@ enum {
4444
REQUEST_BY_NODE,
4545
};
4646

47-
static inline u32 __omap_dm_timer_read(struct omap_dm_timer *timer, u32 reg,
48-
int posted)
47+
/**
48+
* dmtimer_read - read timer registers in posted and non-posted mode
49+
* @timer: timer pointer over which read operation to perform
50+
* @reg: lowest byte holds the register offset
51+
*
52+
* The posted mode bit is encoded in reg. Note that in posted mode, write
53+
* pending bit must be checked. Otherwise a read of a non completed write
54+
* will produce an error.
55+
*/
56+
static inline u32 dmtimer_read(struct omap_dm_timer *timer, u32 reg)
4957
{
50-
if (posted)
51-
while (readl_relaxed(timer->pend) & (reg >> WPSHIFT))
58+
u16 wp, offset;
59+
60+
wp = reg >> WPSHIFT;
61+
offset = reg & 0xff;
62+
63+
/* Wait for a possible write pending bit in posted mode */
64+
if (wp && timer->posted)
65+
while (readl_relaxed(timer->pend) & wp)
5266
cpu_relax();
5367

54-
return readl_relaxed(timer->func_base + (reg & 0xff));
68+
return readl_relaxed(timer->func_base + offset);
5569
}
5670

5771
static inline void __omap_dm_timer_write(struct omap_dm_timer *timer,
@@ -121,13 +135,13 @@ static inline void __omap_dm_timer_stop(struct omap_dm_timer *timer,
121135
{
122136
u32 l;
123137

124-
l = __omap_dm_timer_read(timer, OMAP_TIMER_CTRL_REG, posted);
138+
l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG);
125139
if (l & OMAP_TIMER_CTRL_ST) {
126140
l &= ~0x1;
127141
__omap_dm_timer_write(timer, OMAP_TIMER_CTRL_REG, l, posted);
128142
#ifdef CONFIG_ARCH_OMAP2PLUS
129143
/* Readback to make sure write has completed */
130-
__omap_dm_timer_read(timer, OMAP_TIMER_CTRL_REG, posted);
144+
dmtimer_read(timer, OMAP_TIMER_CTRL_REG);
131145
/*
132146
* Wait for functional clock period x 3.5 to make sure that
133147
* timer is stopped
@@ -148,9 +162,9 @@ static inline void __omap_dm_timer_int_enable(struct omap_dm_timer *timer,
148162
}
149163

150164
static inline unsigned int
151-
__omap_dm_timer_read_counter(struct omap_dm_timer *timer, int posted)
165+
__omap_dm_timer_read_counter(struct omap_dm_timer *timer)
152166
{
153-
return __omap_dm_timer_read(timer, OMAP_TIMER_COUNTER_REG, posted);
167+
return dmtimer_read(timer, OMAP_TIMER_COUNTER_REG);
154168
}
155169

156170
static inline void __omap_dm_timer_write_status(struct omap_dm_timer *timer,
@@ -159,21 +173,6 @@ static inline void __omap_dm_timer_write_status(struct omap_dm_timer *timer,
159173
writel_relaxed(value, timer->irq_stat);
160174
}
161175

162-
/**
163-
* omap_dm_timer_read_reg - read timer registers in posted and non-posted mode
164-
* @timer: timer pointer over which read operation to perform
165-
* @reg: lowest byte holds the register offset
166-
*
167-
* The posted mode bit is encoded in reg. Note that in posted mode write
168-
* pending bit must be checked. Otherwise a read of a non completed write
169-
* will produce an error.
170-
*/
171-
static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, u32 reg)
172-
{
173-
WARN_ON((reg & 0xff) < _OMAP_TIMER_WAKEUP_EN_OFFSET);
174-
return __omap_dm_timer_read(timer, reg, timer->posted);
175-
}
176-
177176
/**
178177
* omap_dm_timer_write_reg - write timer registers in posted and non-posted mode
179178
* @timer: timer pointer over which write operation is to perform
@@ -213,20 +212,14 @@ static void omap_timer_restore_context(struct omap_dm_timer *timer)
213212

214213
static void omap_timer_save_context(struct omap_dm_timer *timer)
215214
{
216-
timer->context.ocp_cfg =
217-
__omap_dm_timer_read(timer, OMAP_TIMER_OCP_CFG_OFFSET, 0);
218-
219-
timer->context.tclr =
220-
omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
221-
timer->context.twer =
222-
omap_dm_timer_read_reg(timer, OMAP_TIMER_WAKEUP_EN_REG);
223-
timer->context.tldr =
224-
omap_dm_timer_read_reg(timer, OMAP_TIMER_LOAD_REG);
225-
timer->context.tmar =
226-
omap_dm_timer_read_reg(timer, OMAP_TIMER_MATCH_REG);
215+
timer->context.ocp_cfg = dmtimer_read(timer, OMAP_TIMER_OCP_CFG_OFFSET);
216+
217+
timer->context.tclr = dmtimer_read(timer, OMAP_TIMER_CTRL_REG);
218+
timer->context.twer = dmtimer_read(timer, OMAP_TIMER_WAKEUP_EN_REG);
219+
timer->context.tldr = dmtimer_read(timer, OMAP_TIMER_LOAD_REG);
220+
timer->context.tmar = dmtimer_read(timer, OMAP_TIMER_MATCH_REG);
227221
timer->context.tier = readl_relaxed(timer->irq_ena);
228-
timer->context.tsicr =
229-
omap_dm_timer_read_reg(timer, OMAP_TIMER_IF_CTRL_REG);
222+
timer->context.tsicr = dmtimer_read(timer, OMAP_TIMER_IF_CTRL_REG);
230223
}
231224

232225
static int omap_timer_context_notifier(struct notifier_block *nb,
@@ -266,8 +259,7 @@ static int omap_dm_timer_reset(struct omap_dm_timer *timer)
266259
omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
267260

268261
do {
269-
l = __omap_dm_timer_read(timer,
270-
OMAP_TIMER_V1_SYS_STAT_OFFSET, 0);
262+
l = dmtimer_read(timer, OMAP_TIMER_V1_SYS_STAT_OFFSET);
271263
} while (!l && timeout--);
272264

273265
if (!timeout) {
@@ -276,7 +268,7 @@ static int omap_dm_timer_reset(struct omap_dm_timer *timer)
276268
}
277269

278270
/* Configure timer for smart-idle mode */
279-
l = __omap_dm_timer_read(timer, OMAP_TIMER_OCP_CFG_OFFSET, 0);
271+
l = dmtimer_read(timer, OMAP_TIMER_OCP_CFG_OFFSET);
280272
l |= 0x2 << 0x3;
281273
__omap_dm_timer_write(timer, OMAP_TIMER_OCP_CFG_OFFSET, l, 0);
282274

@@ -550,7 +542,7 @@ __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
550542
list_for_each_entry(timer, &omap_timer_list, node) {
551543
u32 l;
552544

553-
l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
545+
l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG);
554546
if (l & OMAP_TIMER_CTRL_ST) {
555547
if (((omap_readl(MOD_CONF_CTRL_1) >> (i * 2)) & 0x03) == 0)
556548
inputmask &= ~(1 << 1);
@@ -591,7 +583,7 @@ static int omap_dm_timer_start(struct omap_dm_timer *timer)
591583

592584
omap_dm_timer_enable(timer);
593585

594-
l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
586+
l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG);
595587
if (!(l & OMAP_TIMER_CTRL_ST)) {
596588
l |= OMAP_TIMER_CTRL_ST;
597589
omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
@@ -638,7 +630,7 @@ static int omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable,
638630
return -EINVAL;
639631

640632
omap_dm_timer_enable(timer);
641-
l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
633+
l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG);
642634
if (enable)
643635
l |= OMAP_TIMER_CTRL_CE;
644636
else
@@ -659,7 +651,7 @@ static int omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on,
659651
return -EINVAL;
660652

661653
omap_dm_timer_enable(timer);
662-
l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
654+
l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG);
663655
l &= ~(OMAP_TIMER_CTRL_GPOCFG | OMAP_TIMER_CTRL_SCPWM |
664656
OMAP_TIMER_CTRL_PT | (0x03 << 10) | OMAP_TIMER_CTRL_AR);
665657
if (def_on)
@@ -683,7 +675,7 @@ static int omap_dm_timer_get_pwm_status(struct omap_dm_timer *timer)
683675
return -EINVAL;
684676

685677
omap_dm_timer_enable(timer);
686-
l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
678+
l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG);
687679
omap_dm_timer_disable(timer);
688680

689681
return l;
@@ -698,7 +690,7 @@ static int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer,
698690
return -EINVAL;
699691

700692
omap_dm_timer_enable(timer);
701-
l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
693+
l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG);
702694
l &= ~(OMAP_TIMER_CTRL_PRE | (0x07 << 2));
703695
if (prescaler >= 0) {
704696
l |= OMAP_TIMER_CTRL_PRE;
@@ -743,7 +735,7 @@ static int omap_dm_timer_set_int_disable(struct omap_dm_timer *timer, u32 mask)
743735
l = readl_relaxed(timer->irq_ena) & ~mask;
744736

745737
writel_relaxed(l, timer->irq_dis);
746-
l = omap_dm_timer_read_reg(timer, OMAP_TIMER_WAKEUP_EN_REG) & ~mask;
738+
l = dmtimer_read(timer, OMAP_TIMER_WAKEUP_EN_REG) & ~mask;
747739
omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, l);
748740

749741
omap_dm_timer_disable(timer);
@@ -781,7 +773,7 @@ static unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer)
781773
return 0;
782774
}
783775

784-
return __omap_dm_timer_read_counter(timer, timer->posted);
776+
return __omap_dm_timer_read_counter(timer);
785777
}
786778

787779
static int omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value)

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