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Merge tag 'clk-divider-round-rate-v6.20-v2' of https://github.com/masneyb/linux into clk-divider
Pull divider_round_rate() and friends removal series from Brian Masney: Here's a series that lays the groundwork to rid of the deprecated APIs divider_round_rate(), divider_round_rate_parent(), and divider_ro_round_rate_parent() since these functions are just wrappers for the determine_rate variant. We need to wait for some other changes to land in Linus's tree via the phy tree before we can actually remove these functions. We should be able to do that during the next development cycle. Note that when I converted some of these drivers from round_rate to determine_rate, this was mistakenly converted to the following in some cases: req->rate = divider_round_rate(...) This is invalid in the case when an error occurs since it can set the rate to a negative value. So this series fixes those bugs and removes the deprecated APIs all in one go. Note that this also contains a clk-specific change to drivers/rtc/rtc-ac100.c, and that patch carrys an Acked-by from Alexandre. * tag 'clk-divider-round-rate-v6.20-v2' of https://github.com/masneyb/linux: rtc: ac100: convert from divider_round_rate() to divider_determine_rate() clk: zynqmp: divider: convert from divider_round_rate() to divider_determine_rate() clk: x86: cgu: convert from divider_round_rate() to divider_determine_rate() clk: versaclock3: convert from divider_round_rate() to divider_determine_rate() clk: stm32: stm32-core: convert from divider_round_rate_parent() to divider_determine_rate() clk: stm32: stm32-core: convert from divider_ro_round_rate() to divider_ro_determine_rate() clk: sprd: div: convert from divider_round_rate() to divider_determine_rate() clk: sophgo: sg2042-clkgen: convert from divider_round_rate() to divider_determine_rate() clk: nxp: lpc32xx: convert from divider_round_rate() to divider_determine_rate() clk: nuvoton: ma35d1-divider: convert from divider_round_rate() to divider_determine_rate() clk: milbeaut: convert from divider_round_rate() to divider_determine_rate() clk: milbeaut: convert from divider_ro_round_rate() to divider_ro_determine_rate() clk: loongson1: convert from divider_round_rate() to divider_determine_rate() clk: hisilicon: clkdivider-hi6220: convert from divider_round_rate() to divider_determine_rate() clk: bm1880: convert from divider_round_rate() to divider_determine_rate() clk: bm1880: convert from divider_ro_round_rate() to divider_ro_determine_rate() clk: actions: owl-divider: convert from divider_round_rate() to divider_determine_rate() clk: actions: owl-composite: convert from owl_divider_helper_round_rate() to divider_determine_rate() clk: sunxi-ng: convert from divider_round_rate_parent() to divider_determine_rate() clk: sophgo: cv18xx-ip: convert from divider_round_rate() to divider_determine_rate()
2 parents 8f0b4cc + ed80624 commit 9160ca4

23 files changed

Lines changed: 245 additions & 299 deletions

drivers/clk/actions/owl-composite.c

Lines changed: 3 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -57,15 +57,10 @@ static int owl_comp_div_determine_rate(struct clk_hw *hw,
5757
struct clk_rate_request *req)
5858
{
5959
struct owl_composite *comp = hw_to_owl_comp(hw);
60-
long rate;
61-
62-
rate = owl_divider_helper_round_rate(&comp->common, &comp->rate.div_hw,
63-
req->rate, &req->best_parent_rate);
64-
if (rate < 0)
65-
return rate;
60+
struct owl_divider_hw *div = &comp->rate.div_hw;
6661

67-
req->rate = rate;
68-
return 0;
62+
return divider_determine_rate(&comp->common.hw, req, div->table,
63+
div->width, div->div_flags);
6964
}
7065

7166
static unsigned long owl_comp_div_recalc_rate(struct clk_hw *hw,

drivers/clk/actions/owl-divider.c

Lines changed: 2 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -13,26 +13,13 @@
1313

1414
#include "owl-divider.h"
1515

16-
long owl_divider_helper_round_rate(struct owl_clk_common *common,
17-
const struct owl_divider_hw *div_hw,
18-
unsigned long rate,
19-
unsigned long *parent_rate)
20-
{
21-
return divider_round_rate(&common->hw, rate, parent_rate,
22-
div_hw->table, div_hw->width,
23-
div_hw->div_flags);
24-
}
25-
2616
static int owl_divider_determine_rate(struct clk_hw *hw,
2717
struct clk_rate_request *req)
2818
{
2919
struct owl_divider *div = hw_to_owl_divider(hw);
3020

31-
req->rate = owl_divider_helper_round_rate(&div->common, &div->div_hw,
32-
req->rate,
33-
&req->best_parent_rate);
34-
35-
return 0;
21+
return divider_determine_rate(hw, req, div->div_hw.table,
22+
div->div_hw.width, div->div_hw.div_flags);
3623
}
3724

3825
unsigned long owl_divider_helper_recalc_rate(struct owl_clk_common *common,

drivers/clk/actions/owl-divider.h

Lines changed: 0 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -56,11 +56,6 @@ static inline struct owl_divider *hw_to_owl_divider(struct clk_hw *hw)
5656
return container_of(common, struct owl_divider, common);
5757
}
5858

59-
long owl_divider_helper_round_rate(struct owl_clk_common *common,
60-
const struct owl_divider_hw *div_hw,
61-
unsigned long rate,
62-
unsigned long *parent_rate);
63-
6459
unsigned long owl_divider_helper_recalc_rate(struct owl_clk_common *common,
6560
const struct owl_divider_hw *div_hw,
6661
unsigned long parent_rate);

drivers/clk/clk-bm1880.c

Lines changed: 3 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -621,18 +621,11 @@ static int bm1880_clk_div_determine_rate(struct clk_hw *hw,
621621
val = readl(reg_addr) >> div->shift;
622622
val &= clk_div_mask(div->width);
623623

624-
req->rate = divider_ro_round_rate(hw, req->rate,
625-
&req->best_parent_rate,
626-
div->table,
627-
div->width, div->flags, val);
628-
629-
return 0;
624+
return divider_ro_determine_rate(hw, req, div->table,
625+
div->width, div->flags, val);
630626
}
631627

632-
req->rate = divider_round_rate(hw, req->rate, &req->best_parent_rate,
633-
div->table, div->width, div->flags);
634-
635-
return 0;
628+
return divider_determine_rate(hw, req, div->table, div->width, div->flags);
636629
}
637630

638631
static int bm1880_clk_div_set_rate(struct clk_hw *hw, unsigned long rate,

drivers/clk/clk-loongson1.c

Lines changed: 1 addition & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -99,10 +99,7 @@ static int ls1x_divider_determine_rate(struct clk_hw *hw,
9999
struct ls1x_clk *ls1x_clk = to_ls1x_clk(hw);
100100
const struct ls1x_clk_div_data *d = ls1x_clk->data;
101101

102-
req->rate = divider_round_rate(hw, req->rate, &req->best_parent_rate,
103-
d->table, d->width, d->flags);
104-
105-
return 0;
102+
return divider_determine_rate(hw, req, d->table, d->width, d->flags);
106103
}
107104

108105
static int ls1x_divider_set_rate(struct clk_hw *hw, unsigned long rate,

drivers/clk/clk-milbeaut.c

Lines changed: 4 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -398,19 +398,12 @@ static int m10v_clk_divider_determine_rate(struct clk_hw *hw,
398398
val = readl(divider->reg) >> divider->shift;
399399
val &= clk_div_mask(divider->width);
400400

401-
req->rate = divider_ro_round_rate(hw, req->rate,
402-
&req->best_parent_rate,
403-
divider->table,
404-
divider->width,
405-
divider->flags, val);
406-
407-
return 0;
401+
return divider_ro_determine_rate(hw, req, divider->table,
402+
divider->width, divider->flags,
403+
val);
408404
}
409405

410-
req->rate = divider_round_rate(hw, req->rate, &req->best_parent_rate,
411-
divider->table, divider->width, divider->flags);
412-
413-
return 0;
406+
return divider_determine_rate(hw, req, divider->table, divider->width, divider->flags);
414407
}
415408

416409
static int m10v_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,

drivers/clk/clk-versaclock3.c

Lines changed: 2 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -523,11 +523,8 @@ static int vc3_div_determine_rate(struct clk_hw *hw,
523523
return 0;
524524
}
525525

526-
req->rate = divider_round_rate(hw, req->rate, &req->best_parent_rate,
527-
div_data->table,
528-
div_data->width, div_data->flags);
529-
530-
return 0;
526+
return divider_determine_rate(hw, req, div_data->table, div_data->width,
527+
div_data->flags);
531528
}
532529

533530
static int vc3_div_set_rate(struct clk_hw *hw, unsigned long rate,

drivers/clk/hisilicon/clkdivider-hi6220.c

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -60,10 +60,8 @@ static int hi6220_clkdiv_determine_rate(struct clk_hw *hw,
6060
{
6161
struct hi6220_clk_divider *dclk = to_hi6220_clk_divider(hw);
6262

63-
req->rate = divider_round_rate(hw, req->rate, &req->best_parent_rate, dclk->table,
64-
dclk->width, CLK_DIVIDER_ROUND_CLOSEST);
65-
66-
return 0;
63+
return divider_determine_rate(hw, req, dclk->table, dclk->width,
64+
CLK_DIVIDER_ROUND_CLOSEST);
6765
}
6866

6967
static int hi6220_clkdiv_set_rate(struct clk_hw *hw, unsigned long rate,

drivers/clk/nuvoton/clk-ma35d1-divider.c

Lines changed: 2 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -44,11 +44,8 @@ static int ma35d1_clkdiv_determine_rate(struct clk_hw *hw,
4444
{
4545
struct ma35d1_adc_clk_div *dclk = to_ma35d1_adc_clk_div(hw);
4646

47-
req->rate = divider_round_rate(hw, req->rate, &req->best_parent_rate,
48-
dclk->table, dclk->width,
49-
CLK_DIVIDER_ROUND_CLOSEST);
50-
51-
return 0;
47+
return divider_determine_rate(hw, req, dclk->table, dclk->width,
48+
CLK_DIVIDER_ROUND_CLOSEST);
5249
}
5350

5451
static int ma35d1_clkdiv_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate)

drivers/clk/nxp/clk-lpc32xx.c

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -975,10 +975,8 @@ static int clk_divider_determine_rate(struct clk_hw *hw,
975975
return 0;
976976
}
977977

978-
req->rate = divider_round_rate(hw, req->rate, &req->best_parent_rate,
979-
divider->table, divider->width, divider->flags);
980-
981-
return 0;
978+
return divider_determine_rate(hw, req, divider->table, divider->width,
979+
divider->flags);
982980
}
983981

984982
static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,

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