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Merge tag 'mips_6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux
Pull MIPS updates from Thomas Bogendoerfer: - added support for Huawei B593u-12 - added support for virt board aligned to QEMU MIPS virt board - added support for doing DMA coherence on a per device base - reworked handling of RALINK SoCs - cleanup for Loongon64 barriers - removed deprecated support for MIPS_CMP SMP handling method - removed support Sibyte CARMEL and CHRINE boards - cleanups and fixes * tag 'mips_6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (59 commits) MIPS: uprobes: Restore thread.trap_nr MIPS: Don't clear _PAGE_SPECIAL in _PAGE_CHG_MASK MIPS: Sink body of check_bugs_early() into its only call site MIPS: Mark check_bugs() as __init Revert "MIPS: generic: Enable all CPUs supported by virt board in Kconfig" MIPS: octeon_switch: Remove duplicated labels MIPS: loongson2ef: Add missing break in cs5536_isa MIPS: Remove set_swbp() in uprobes.c MIPS: Use def_bool y for ARCH_SUPPORTS_UPROBES MIPS: fw: Allow firmware to pass a empty env MIPS: Remove deprecated CONFIG_MIPS_CMP MIPS: lantiq: remove unused function declaration MIPS: Drop unused positional parameter in local_irq_{dis,en}able MIPS: mm: Remove local_cache_flush_page MIPS: Remove no longer used ide.h MIPS: mm: Remove unused *cache_page_indexed flush functions MIPS: generic: Enable all CPUs supported by virt board in Kconfig MIPS: Add board config for virt board MIPS: Octeon: Disable CVMSEG by default on other platforms MIPS: Loongson: Don't select platform features with CPU ...
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Lines changed: 657 additions & 1356 deletions

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‎Documentation/devicetree/bindings/mips/loongson/devices.yaml‎

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Original file line numberDiff line numberDiff line change
@@ -37,6 +37,18 @@ properties:
3737
items:
3838
- const: loongson,loongson64v-4core-virtio
3939

40+
- description: LS1B based boards
41+
items:
42+
- enum:
43+
- loongson,lsgz-1b-dev
44+
- const: loongson,ls1b
45+
46+
- description: LS1C based boards
47+
items:
48+
- enum:
49+
- loongmasses,smartloong-1c
50+
- const: loongson,ls1c
51+
4052
additionalProperties: true
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4254
...

‎Documentation/devicetree/bindings/vendor-prefixes.yaml‎

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Original file line numberDiff line numberDiff line change
@@ -777,6 +777,8 @@ patternProperties:
777777
description: Lontium Semiconductor Corporation
778778
"^loongson,.*":
779779
description: Loongson Technology Corporation Limited
780+
"^loongmasses,.*":
781+
description: Nanjing Loongmasses Ltd.
780782
"^lsi,.*":
781783
description: LSI Corp. (LSI Logic)
782784
"^lwn,.*":

‎arch/mips/Kbuild.platforms‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -29,7 +29,6 @@ platform-$(CONFIG_SGI_IP30) += sgi-ip30/
2929
platform-$(CONFIG_SGI_IP32) += sgi-ip32/
3030
platform-$(CONFIG_SIBYTE_BCM112X) += sibyte/
3131
platform-$(CONFIG_SIBYTE_SB1250) += sibyte/
32-
platform-$(CONFIG_SIBYTE_BCM1x55) += sibyte/
3332
platform-$(CONFIG_SIBYTE_BCM1x80) += sibyte/
3433
platform-$(CONFIG_SNI_RM) += sni/
3534
platform-$(CONFIG_MACH_TX49XX) += txx9/

‎arch/mips/Kconfig‎

Lines changed: 6 additions & 71 deletions
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,6 @@ config MIPS
1616
select ARCH_HAS_UBSAN_SANITIZE_ALL
1717
select ARCH_HAS_GCOV_PROFILE_ALL
1818
select ARCH_KEEP_MEMBLOCK
19-
select ARCH_SUPPORTS_UPROBES
2019
select ARCH_USE_BUILTIN_BSWAP
2120
select ARCH_USE_CMPXCHG_LOCKREF if 64BIT
2221
select ARCH_USE_MEMTEST
@@ -113,7 +112,6 @@ config MACH_INGENIC
113112
select SYS_SUPPORTS_LITTLE_ENDIAN
114113
select SYS_SUPPORTS_ZBOOT
115114
select DMA_NONCOHERENT
116-
select ARCH_HAS_SYNC_DMA_FOR_CPU
117115
select IRQ_MIPS_CPU
118116
select PINCTRL
119117
select GPIOLIB
@@ -132,7 +130,6 @@ choice
132130

133131
config MIPS_GENERIC_KERNEL
134132
bool "Generic board-agnostic MIPS kernel"
135-
select ARCH_HAS_SETUP_DMA_OPS
136133
select MIPS_GENERIC
137134
select BOOT_RAW
138135
select BUILTIN_DTB
@@ -488,7 +485,6 @@ config MACH_LOONGSON64
488485
select BOARD_SCACHE
489486
select CSRC_R4K
490487
select CEVT_R4K
491-
select CPU_HAS_WB
492488
select FORCE_PCI
493489
select ISA
494490
select I8259
@@ -565,7 +561,6 @@ config MIPS_MALTA
565561
select SYS_SUPPORTS_LITTLE_ENDIAN
566562
select SYS_SUPPORTS_MICROMIPS
567563
select SYS_SUPPORTS_MIPS16
568-
select SYS_SUPPORTS_MIPS_CMP
569564
select SYS_SUPPORTS_MIPS_CPS
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select SYS_SUPPORTS_MULTITHREADING
571566
select SYS_SUPPORTS_RELOCATABLE
@@ -793,24 +788,6 @@ config SGI_IP32
793788
help
794789
If you want this kernel to run on SGI O2 workstation, say Y here.
795790

796-
config SIBYTE_CRHINE
797-
bool "Sibyte BCM91120C-CRhine"
798-
select BOOT_ELF32
799-
select SIBYTE_BCM1120
800-
select SWAP_IO_SPACE
801-
select SYS_HAS_CPU_SB1
802-
select SYS_SUPPORTS_BIG_ENDIAN
803-
select SYS_SUPPORTS_LITTLE_ENDIAN
804-
805-
config SIBYTE_CARMEL
806-
bool "Sibyte BCM91120x-Carmel"
807-
select BOOT_ELF32
808-
select SIBYTE_BCM1120
809-
select SWAP_IO_SPACE
810-
select SYS_HAS_CPU_SB1
811-
select SYS_SUPPORTS_BIG_ENDIAN
812-
select SYS_SUPPORTS_LITTLE_ENDIAN
813-
814791
config SIBYTE_CRHONE
815792
bool "Sibyte BCM91125C-CRhone"
816793
select BOOT_ELF32
@@ -824,7 +801,7 @@ config SIBYTE_CRHONE
824801
config SIBYTE_RHONE
825802
bool "Sibyte BCM91125E-Rhone"
826803
select BOOT_ELF32
827-
select SIBYTE_BCM1125H
804+
select SIBYTE_SB1250
828805
select SWAP_IO_SPACE
829806
select SYS_HAS_CPU_SB1
830807
select SYS_SUPPORTS_BIG_ENDIAN
@@ -1075,7 +1052,7 @@ config FW_CFE
10751052
bool
10761053

10771054
config ARCH_SUPPORTS_UPROBES
1078-
bool
1055+
def_bool y
10791056

10801057
config DMA_NONCOHERENT
10811058
bool
@@ -1086,8 +1063,10 @@ config DMA_NONCOHERENT
10861063
# by pgprot_writcombine can be mixed, and the latter sometimes provides
10871064
# significant advantages.
10881065
#
1066+
select ARCH_HAS_SETUP_DMA_OPS
10891067
select ARCH_HAS_DMA_WRITE_COMBINE
10901068
select ARCH_HAS_DMA_PREP_COHERENT
1069+
select ARCH_HAS_SYNC_DMA_FOR_CPU
10911070
select ARCH_HAS_SYNC_DMA_FOR_DEVICE
10921071
select ARCH_HAS_DMA_SET_UNCACHED
10931072
select DMA_NONCOHERENT_MMAP
@@ -1181,12 +1160,6 @@ config SYS_SUPPORTS_LITTLE_ENDIAN
11811160
config MIPS_HUGE_TLB_SUPPORT
11821161
def_bool HUGETLB_PAGE || TRANSPARENT_HUGEPAGE
11831162

1184-
config IRQ_MSP_SLP
1185-
bool
1186-
1187-
config IRQ_MSP_CIC
1188-
bool
1189-
11901163
config IRQ_TXX9
11911164
bool
11921165

@@ -1364,7 +1337,6 @@ config CPU_LOONGSON2F
13641337
bool "Loongson 2F"
13651338
depends on SYS_HAS_CPU_LOONGSON2F
13661339
select CPU_LOONGSON2EF
1367-
select GPIOLIB
13681340
help
13691341
The Loongson 2F processor implements the MIPS III instruction set
13701342
with many extensions.
@@ -1786,7 +1758,6 @@ config CPU_LOONGSON2EF
17861758
select CPU_SUPPORTS_64BIT_KERNEL
17871759
select CPU_SUPPORTS_HIGHMEM
17881760
select CPU_SUPPORTS_HUGEPAGES
1789-
select ARCH_HAS_PHYS_TO_DMA
17901761

17911762
config CPU_LOONGSON32
17921763
bool
@@ -1851,11 +1822,9 @@ config SYS_HAS_CPU_MIPS32_R3_5
18511822

18521823
config SYS_HAS_CPU_MIPS32_R5
18531824
bool
1854-
select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
18551825

18561826
config SYS_HAS_CPU_MIPS32_R6
18571827
bool
1858-
select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
18591828

18601829
config SYS_HAS_CPU_MIPS64_R1
18611830
bool
@@ -1865,15 +1834,12 @@ config SYS_HAS_CPU_MIPS64_R2
18651834

18661835
config SYS_HAS_CPU_MIPS64_R5
18671836
bool
1868-
select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
18691837

18701838
config SYS_HAS_CPU_MIPS64_R6
18711839
bool
1872-
select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
18731840

18741841
config SYS_HAS_CPU_P5600
18751842
bool
1876-
select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
18771843

18781844
config SYS_HAS_CPU_R3000
18791845
bool
@@ -1898,7 +1864,6 @@ config SYS_HAS_CPU_NEVADA
18981864

18991865
config SYS_HAS_CPU_R10000
19001866
bool
1901-
select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
19021867

19031868
config SYS_HAS_CPU_RM7000
19041869
bool
@@ -1927,7 +1892,6 @@ config SYS_HAS_CPU_BMIPS4380
19271892
config SYS_HAS_CPU_BMIPS5000
19281893
bool
19291894
select SYS_HAS_CPU_BMIPS
1930-
select ARCH_HAS_SYNC_DMA_FOR_CPU
19311895

19321896
#
19331897
# CPU may reorder R->R, R->W, W->R, W->W
@@ -2298,15 +2262,10 @@ config MIPS_VPE_LOADER
22982262
Includes a loader for loading an elf relocatable object
22992263
onto another VPE and running it.
23002264

2301-
config MIPS_VPE_LOADER_CMP
2302-
bool
2303-
default "y"
2304-
depends on MIPS_VPE_LOADER && MIPS_CMP
2305-
23062265
config MIPS_VPE_LOADER_MT
23072266
bool
23082267
default "y"
2309-
depends on MIPS_VPE_LOADER && !MIPS_CMP
2268+
depends on MIPS_VPE_LOADER
23102269

23112270
config MIPS_VPE_LOADER_TOM
23122271
bool "Load VPE program into memory hidden from linux"
@@ -2322,31 +2281,10 @@ config MIPS_VPE_APSP_API
23222281
bool "Enable support for AP/SP API (RTLX)"
23232282
depends on MIPS_VPE_LOADER
23242283

2325-
config MIPS_VPE_APSP_API_CMP
2326-
bool
2327-
default "y"
2328-
depends on MIPS_VPE_APSP_API && MIPS_CMP
2329-
23302284
config MIPS_VPE_APSP_API_MT
23312285
bool
23322286
default "y"
2333-
depends on MIPS_VPE_APSP_API && !MIPS_CMP
2334-
2335-
config MIPS_CMP
2336-
bool "MIPS CMP framework support (DEPRECATED)"
2337-
depends on SYS_SUPPORTS_MIPS_CMP && !CPU_MIPSR6
2338-
select SMP
2339-
select SYNC_R4K
2340-
select SYS_SUPPORTS_SMP
2341-
select WEAK_ORDERING
2342-
default n
2343-
help
2344-
Select this if you are using a bootloader which implements the "CMP
2345-
framework" protocol (ie. YAMON) and want your kernel to make use of
2346-
its ability to start secondary CPUs.
2347-
2348-
Unless you have a specific need, you should use CONFIG_MIPS_CPS
2349-
instead of this.
2287+
depends on MIPS_VPE_APSP_API
23502288

23512289
config MIPS_CPS
23522290
bool "MIPS Coherent Processing System support"
@@ -2802,9 +2740,6 @@ config HOTPLUG_CPU
28022740
config SMP_UP
28032741
bool
28042742

2805-
config SYS_SUPPORTS_MIPS_CMP
2806-
bool
2807-
28082743
config SYS_SUPPORTS_MIPS_CPS
28092744
bool
28102745

‎arch/mips/Makefile‎

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Original file line numberDiff line numberDiff line change
@@ -181,9 +181,47 @@ endif
181181
cflags-$(CONFIG_CAVIUM_CN63XXP1) += -Wa,-mfix-cn63xxp1
182182
cflags-$(CONFIG_CPU_BMIPS) += -march=mips32 -Wa,-mips32 -Wa,--trap
183183

184+
cflags-$(CONFIG_CPU_LOONGSON2E) += -march=loongson2e -Wa,--trap
185+
cflags-$(CONFIG_CPU_LOONGSON2F) += -march=loongson2f -Wa,--trap
186+
# Some -march= flags enable MMI instructions, and GCC complains about that
187+
# support being enabled alongside -msoft-float. Thus explicitly disable MMI.
188+
cflags-$(CONFIG_CPU_LOONGSON2EF) += $(call cc-option,-mno-loongson-mmi)
189+
ifdef CONFIG_CPU_LOONGSON64
190+
cflags-$(CONFIG_CPU_LOONGSON64) += -Wa,--trap
191+
cflags-$(CONFIG_CC_IS_GCC) += -march=loongson3a
192+
cflags-$(CONFIG_CC_IS_CLANG) += -march=mips64r2
193+
endif
194+
cflags-$(CONFIG_CPU_LOONGSON64) += $(call cc-option,-mno-loongson-mmi)
195+
184196
cflags-$(CONFIG_CPU_R4000_WORKAROUNDS) += $(call cc-option,-mfix-r4000,)
185197
cflags-$(CONFIG_CPU_R4400_WORKAROUNDS) += $(call cc-option,-mfix-r4400,)
186198
cflags-$(CONFIG_CPU_DADDI_WORKAROUNDS) += $(call cc-option,-mno-daddi,)
199+
ifdef CONFIG_CPU_LOONGSON2F_WORKAROUNDS
200+
cflags-$(CONFIG_CPU_NOP_WORKAROUNDS) += -Wa,-mfix-loongson2f-nop
201+
cflags-$(CONFIG_CPU_JUMP_WORKAROUNDS) += -Wa,-mfix-loongson2f-jump
202+
endif
203+
204+
#
205+
# Some versions of binutils, not currently mainline as of 2019/02/04, support
206+
# an -mfix-loongson3-llsc flag which emits a sync prior to each ll instruction
207+
# to work around a CPU bug (see __SYNC_loongson3_war in asm/sync.h for a
208+
# description).
209+
#
210+
# We disable this in order to prevent the assembler meddling with the
211+
# instruction that labels refer to, ie. if we label an ll instruction:
212+
#
213+
# 1: ll v0, 0(a0)
214+
#
215+
# ...then with the assembler fix applied the label may actually point at a sync
216+
# instruction inserted by the assembler, and if we were using the label in an
217+
# exception table the table would no longer contain the address of the ll
218+
# instruction.
219+
#
220+
# Avoid this by explicitly disabling that assembler behaviour. If upstream
221+
# binutils does not merge support for the flag then we can revisit & remove
222+
# this later - for now it ensures vendor toolchains don't cause problems.
223+
#
224+
cflags-$(CONFIG_CPU_LOONGSON64) += $(call as-option,-Wa$(comma)-mno-fix-loongson3-llsc,)
187225

188226
# For smartmips configurations, there are hundreds of warnings due to ISA overrides
189227
# in assembly and header files. smartmips is only supported for MIPS32r1 onwards

‎arch/mips/ath79/Kconfig‎

Lines changed: 0 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -29,20 +29,4 @@ config SOC_QCA955X
2929
config PCI_AR724X
3030
def_bool n
3131

32-
config ATH79_DEV_GPIO_BUTTONS
33-
def_bool n
34-
35-
config ATH79_DEV_LEDS_GPIO
36-
def_bool n
37-
38-
config ATH79_DEV_SPI
39-
def_bool n
40-
41-
config ATH79_DEV_USB
42-
def_bool n
43-
44-
config ATH79_DEV_WMAC
45-
depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA955X)
46-
def_bool n
47-
4832
endif

‎arch/mips/bcm47xx/board.c‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -193,6 +193,7 @@ struct bcm47xx_board_type_list1 bcm47xx_board_list_board_id[] __initconst = {
193193
/* boardtype, boardnum, boardrev */
194194
static const
195195
struct bcm47xx_board_type_list3 bcm47xx_board_list_board[] __initconst = {
196+
{{BCM47XX_BOARD_HUAWEI_B593U_12, "Huawei B593u-12"}, "0x053d", "1234", "0x1301"},
196197
{{BCM47XX_BOARD_HUAWEI_E970, "Huawei E970"}, "0x048e", "0x5347", "0x11"},
197198
{{BCM47XX_BOARD_PHICOMM_M1, "Phicomm M1"}, "0x0590", "80", "0x1104"},
198199
{{BCM47XX_BOARD_ZTE_H218N, "ZTE H218N"}, "0x053d", "1234", "0x1305"},

‎arch/mips/bcm47xx/leds.c‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -222,6 +222,11 @@ bcm47xx_leds_dlink_dir330[] __initconst = {
222222

223223
/* Huawei */
224224

225+
static const struct gpio_led
226+
bcm47xx_leds_huawei_b593u_12[] __initconst = {
227+
BCM47XX_GPIO_LED(5, "blue", "wlan", 0, LEDS_GPIO_DEFSTATE_OFF),
228+
};
229+
225230
static const struct gpio_led
226231
bcm47xx_leds_huawei_e970[] __initconst = {
227232
BCM47XX_GPIO_LED(0, "unk", "wlan", 0, LEDS_GPIO_DEFSTATE_OFF),
@@ -672,6 +677,9 @@ void __init bcm47xx_leds_register(void)
672677
bcm47xx_set_pdata(bcm47xx_leds_dlink_dir330);
673678
break;
674679

680+
case BCM47XX_BOARD_HUAWEI_B593U_12:
681+
bcm47xx_set_pdata(bcm47xx_leds_huawei_b593u_12);
682+
break;
675683
case BCM47XX_BOARD_HUAWEI_E970:
676684
bcm47xx_set_pdata(bcm47xx_leds_huawei_e970);
677685
break;

‎arch/mips/cavium-octeon/Kconfig‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,8 @@ config CAVIUM_CN63XXP1
1414
config CAVIUM_OCTEON_CVMSEG_SIZE
1515
int "Number of L1 cache lines reserved for CVMSEG memory"
1616
range 0 54
17-
default 1
17+
default 0 if !CAVIUM_OCTEON_SOC
18+
default 1 if CAVIUM_OCTEON_SOC
1819
help
1920
CVMSEG LM is a segment that accesses portions of the dcache as a
2021
local memory; the larger CVMSEG is, the smaller the cache is.

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