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31 | 31 | { FORCEWAKE_MT, 0, 0, "FORCEWAKE" } |
32 | 32 |
|
33 | 33 | #define COMMON_GEN9BASE_GLOBAL \ |
34 | | - { GEN8_FAULT_TLB_DATA0, 0, 0, "GEN8_FAULT_TLB_DATA0" }, \ |
35 | | - { GEN8_FAULT_TLB_DATA1, 0, 0, "GEN8_FAULT_TLB_DATA1" }, \ |
36 | 34 | { ERROR_GEN6, 0, 0, "ERROR_GEN6" }, \ |
37 | 35 | { DONE_REG, 0, 0, "DONE_REG" }, \ |
38 | 36 | { HSW_GTT_CACHE_EN, 0, 0, "HSW_GTT_CACHE_EN" } |
39 | 37 |
|
| 38 | +#define GEN9_GLOBAL \ |
| 39 | + { GEN8_FAULT_TLB_DATA0, 0, 0, "GEN8_FAULT_TLB_DATA0" }, \ |
| 40 | + { GEN8_FAULT_TLB_DATA1, 0, 0, "GEN8_FAULT_TLB_DATA1" } |
| 41 | + |
40 | 42 | #define COMMON_GEN12BASE_GLOBAL \ |
41 | 43 | { GEN12_FAULT_TLB_DATA0, 0, 0, "GEN12_FAULT_TLB_DATA0" }, \ |
42 | 44 | { GEN12_FAULT_TLB_DATA1, 0, 0, "GEN12_FAULT_TLB_DATA1" }, \ |
@@ -142,6 +144,7 @@ static const struct __guc_mmio_reg_descr xe_lpd_gsc_inst_regs[] = { |
142 | 144 | static const struct __guc_mmio_reg_descr default_global_regs[] = { |
143 | 145 | COMMON_BASE_GLOBAL, |
144 | 146 | COMMON_GEN9BASE_GLOBAL, |
| 147 | + GEN9_GLOBAL, |
145 | 148 | }; |
146 | 149 |
|
147 | 150 | static const struct __guc_mmio_reg_descr default_rc_class_regs[] = { |
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