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pinctrl: rk805: Add rk806 pinctrl support
Add support for rk806 dvs pinctrl to the existing rk805 driver. This has been implemented using shengfei Xu's rk806 specific driver from the vendor tree as reference. Co-developed-by: shengfei Xu <xsf@rock-chips.com> Signed-off-by: shengfei Xu <xsf@rock-chips.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Tested-by: Diederik de Haas <didi.debian@cknow.org> # Rock64, Quartz64 Model A + B Tested-by: Vincent Legoll <vincent.legoll@gmail.com> # Pine64 QuartzPro64 Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20230504173618.142075-10-sebastian.reichel@collabora.com Signed-off-by: Lee Jones <lee@kernel.org>
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Lines changed: 168 additions & 21 deletions

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‎drivers/pinctrl/pinctrl-rk805.c‎

Lines changed: 168 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,12 @@
11
// SPDX-License-Identifier: GPL-2.0-or-later
22
/*
3-
* Pinctrl driver for Rockchip RK805 PMIC
3+
* Pinctrl driver for Rockchip RK805/RK806 PMIC
44
*
55
* Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd
6+
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
67
*
78
* Author: Joseph Chen <chenjh@rock-chips.com>
9+
* Author: Xu Shengfei <xsf@rock-chips.com>
810
*
911
* Based on the pinctrl-as3722 driver
1012
*/
@@ -44,6 +46,7 @@ struct rk805_pin_group {
4446

4547
/*
4648
* @reg: gpio setting register;
49+
* @fun_reg: functions select register;
4750
* @fun_mask: functions select mask value, when set is gpio;
4851
* @dir_mask: input or output mask value, when set is output, otherwise input;
4952
* @val_mask: gpio set value, when set is level high, otherwise low;
@@ -56,6 +59,7 @@ struct rk805_pin_group {
5659
*/
5760
struct rk805_pin_config {
5861
u8 reg;
62+
u8 fun_reg;
5963
u8 fun_msk;
6064
u8 dir_msk;
6165
u8 val_msk;
@@ -80,22 +84,50 @@ enum rk805_pinmux_option {
8084
RK805_PINMUX_GPIO,
8185
};
8286

87+
enum rk806_pinmux_option {
88+
RK806_PINMUX_FUN0 = 0,
89+
RK806_PINMUX_FUN1,
90+
RK806_PINMUX_FUN2,
91+
RK806_PINMUX_FUN3,
92+
RK806_PINMUX_FUN4,
93+
RK806_PINMUX_FUN5,
94+
};
95+
8396
enum {
8497
RK805_GPIO0,
8598
RK805_GPIO1,
8699
};
87100

101+
enum {
102+
RK806_GPIO_DVS1,
103+
RK806_GPIO_DVS2,
104+
RK806_GPIO_DVS3
105+
};
106+
88107
static const char *const rk805_gpio_groups[] = {
89108
"gpio0",
90109
"gpio1",
91110
};
92111

112+
static const char *const rk806_gpio_groups[] = {
113+
"gpio_pwrctrl1",
114+
"gpio_pwrctrl2",
115+
"gpio_pwrctrl3",
116+
};
117+
93118
/* RK805: 2 output only GPIOs */
94119
static const struct pinctrl_pin_desc rk805_pins_desc[] = {
95120
PINCTRL_PIN(RK805_GPIO0, "gpio0"),
96121
PINCTRL_PIN(RK805_GPIO1, "gpio1"),
97122
};
98123

124+
/* RK806 */
125+
static const struct pinctrl_pin_desc rk806_pins_desc[] = {
126+
PINCTRL_PIN(RK806_GPIO_DVS1, "gpio_pwrctrl1"),
127+
PINCTRL_PIN(RK806_GPIO_DVS2, "gpio_pwrctrl2"),
128+
PINCTRL_PIN(RK806_GPIO_DVS3, "gpio_pwrctrl3"),
129+
};
130+
99131
static const struct rk805_pin_function rk805_pin_functions[] = {
100132
{
101133
.name = "gpio",
@@ -105,6 +137,45 @@ static const struct rk805_pin_function rk805_pin_functions[] = {
105137
},
106138
};
107139

140+
static const struct rk805_pin_function rk806_pin_functions[] = {
141+
{
142+
.name = "pin_fun0",
143+
.groups = rk806_gpio_groups,
144+
.ngroups = ARRAY_SIZE(rk806_gpio_groups),
145+
.mux_option = RK806_PINMUX_FUN0,
146+
},
147+
{
148+
.name = "pin_fun1",
149+
.groups = rk806_gpio_groups,
150+
.ngroups = ARRAY_SIZE(rk806_gpio_groups),
151+
.mux_option = RK806_PINMUX_FUN1,
152+
},
153+
{
154+
.name = "pin_fun2",
155+
.groups = rk806_gpio_groups,
156+
.ngroups = ARRAY_SIZE(rk806_gpio_groups),
157+
.mux_option = RK806_PINMUX_FUN2,
158+
},
159+
{
160+
.name = "pin_fun3",
161+
.groups = rk806_gpio_groups,
162+
.ngroups = ARRAY_SIZE(rk806_gpio_groups),
163+
.mux_option = RK806_PINMUX_FUN3,
164+
},
165+
{
166+
.name = "pin_fun4",
167+
.groups = rk806_gpio_groups,
168+
.ngroups = ARRAY_SIZE(rk806_gpio_groups),
169+
.mux_option = RK806_PINMUX_FUN4,
170+
},
171+
{
172+
.name = "pin_fun5",
173+
.groups = rk806_gpio_groups,
174+
.ngroups = ARRAY_SIZE(rk806_gpio_groups),
175+
.mux_option = RK806_PINMUX_FUN5,
176+
},
177+
};
178+
108179
static const struct rk805_pin_group rk805_pin_groups[] = {
109180
{
110181
.name = "gpio0",
@@ -118,6 +189,24 @@ static const struct rk805_pin_group rk805_pin_groups[] = {
118189
},
119190
};
120191

192+
static const struct rk805_pin_group rk806_pin_groups[] = {
193+
{
194+
.name = "gpio_pwrctrl1",
195+
.pins = { RK806_GPIO_DVS1 },
196+
.npins = 1,
197+
},
198+
{
199+
.name = "gpio_pwrctrl2",
200+
.pins = { RK806_GPIO_DVS2 },
201+
.npins = 1,
202+
},
203+
{
204+
.name = "gpio_pwrctrl3",
205+
.pins = { RK806_GPIO_DVS3 },
206+
.npins = 1,
207+
}
208+
};
209+
121210
#define RK805_GPIO0_VAL_MSK BIT(0)
122211
#define RK805_GPIO1_VAL_MSK BIT(1)
123212

@@ -132,6 +221,40 @@ static const struct rk805_pin_config rk805_gpio_cfgs[] = {
132221
},
133222
};
134223

224+
#define RK806_PWRCTRL1_DR BIT(0)
225+
#define RK806_PWRCTRL2_DR BIT(1)
226+
#define RK806_PWRCTRL3_DR BIT(2)
227+
#define RK806_PWRCTRL1_DATA BIT(4)
228+
#define RK806_PWRCTRL2_DATA BIT(5)
229+
#define RK806_PWRCTRL3_DATA BIT(6)
230+
#define RK806_PWRCTRL1_FUN GENMASK(2, 0)
231+
#define RK806_PWRCTRL2_FUN GENMASK(6, 4)
232+
#define RK806_PWRCTRL3_FUN GENMASK(2, 0)
233+
234+
static struct rk805_pin_config rk806_gpio_cfgs[] = {
235+
{
236+
.fun_reg = RK806_SLEEP_CONFIG0,
237+
.fun_msk = RK806_PWRCTRL1_FUN,
238+
.reg = RK806_SLEEP_GPIO,
239+
.val_msk = RK806_PWRCTRL1_DATA,
240+
.dir_msk = RK806_PWRCTRL1_DR,
241+
},
242+
{
243+
.fun_reg = RK806_SLEEP_CONFIG0,
244+
.fun_msk = RK806_PWRCTRL2_FUN,
245+
.reg = RK806_SLEEP_GPIO,
246+
.val_msk = RK806_PWRCTRL2_DATA,
247+
.dir_msk = RK806_PWRCTRL2_DR,
248+
},
249+
{
250+
.fun_reg = RK806_SLEEP_CONFIG1,
251+
.fun_msk = RK806_PWRCTRL3_FUN,
252+
.reg = RK806_SLEEP_GPIO,
253+
.val_msk = RK806_PWRCTRL3_DATA,
254+
.dir_msk = RK806_PWRCTRL3_DR,
255+
}
256+
};
257+
135258
/* generic gpio chip */
136259
static int rk805_gpio_get(struct gpio_chip *chip, unsigned int offset)
137260
{
@@ -289,19 +412,13 @@ static int _rk805_pinctrl_set_mux(struct pinctrl_dev *pctldev,
289412
if (!pci->pin_cfg[offset].fun_msk)
290413
return 0;
291414

292-
if (mux == RK805_PINMUX_GPIO) {
293-
ret = regmap_update_bits(pci->rk808->regmap,
294-
pci->pin_cfg[offset].reg,
295-
pci->pin_cfg[offset].fun_msk,
296-
pci->pin_cfg[offset].fun_msk);
297-
if (ret) {
298-
dev_err(pci->dev, "set gpio%d GPIO failed\n", offset);
299-
return ret;
300-
}
301-
} else {
302-
dev_err(pci->dev, "Couldn't find function mux %d\n", mux);
303-
return -EINVAL;
304-
}
415+
mux <<= ffs(pci->pin_cfg[offset].fun_msk) - 1;
416+
ret = regmap_update_bits(pci->rk808->regmap,
417+
pci->pin_cfg[offset].fun_reg,
418+
pci->pin_cfg[offset].fun_msk, mux);
419+
420+
if (ret)
421+
dev_err(pci->dev, "set gpio%d func%d failed\n", offset, mux);
305422

306423
return 0;
307424
}
@@ -317,20 +434,29 @@ static int rk805_pinctrl_set_mux(struct pinctrl_dev *pctldev,
317434
return _rk805_pinctrl_set_mux(pctldev, offset, mux);
318435
}
319436

437+
static int rk805_pinctrl_gpio_request_enable(struct pinctrl_dev *pctldev,
438+
struct pinctrl_gpio_range *range,
439+
unsigned int offset)
440+
{
441+
struct rk805_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev);
442+
443+
switch (pci->rk808->variant) {
444+
case RK805_ID:
445+
return _rk805_pinctrl_set_mux(pctldev, offset, RK805_PINMUX_GPIO);
446+
case RK806_ID:
447+
return _rk805_pinctrl_set_mux(pctldev, offset, RK806_PINMUX_FUN5);
448+
}
449+
450+
return -ENOTSUPP;
451+
}
452+
320453
static int rk805_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
321454
struct pinctrl_gpio_range *range,
322455
unsigned int offset, bool input)
323456
{
324457
struct rk805_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev);
325458
int ret;
326459

327-
/* switch to gpio function */
328-
ret = _rk805_pinctrl_set_mux(pctldev, offset, RK805_PINMUX_GPIO);
329-
if (ret) {
330-
dev_err(pci->dev, "set gpio%d mux failed\n", offset);
331-
return ret;
332-
}
333-
334460
/* set direction */
335461
if (!pci->pin_cfg[offset].dir_msk)
336462
return 0;
@@ -352,6 +478,7 @@ static const struct pinmux_ops rk805_pinmux_ops = {
352478
.get_function_name = rk805_pinctrl_get_func_name,
353479
.get_function_groups = rk805_pinctrl_get_func_groups,
354480
.set_mux = rk805_pinctrl_set_mux,
481+
.gpio_request_enable = rk805_pinctrl_gpio_request_enable,
355482
.gpio_set_direction = rk805_pmx_gpio_set_direction,
356483
};
357484

@@ -364,6 +491,7 @@ static int rk805_pinconf_get(struct pinctrl_dev *pctldev,
364491

365492
switch (param) {
366493
case PIN_CONFIG_OUTPUT:
494+
case PIN_CONFIG_INPUT_ENABLE:
367495
arg = rk805_gpio_get(&pci->gpio_chip, pin);
368496
break;
369497
default:
@@ -393,6 +521,12 @@ static int rk805_pinconf_set(struct pinctrl_dev *pctldev,
393521
rk805_gpio_set(&pci->gpio_chip, pin, arg);
394522
rk805_pmx_gpio_set_direction(pctldev, NULL, pin, false);
395523
break;
524+
case PIN_CONFIG_INPUT_ENABLE:
525+
if (pci->rk808->variant != RK805_ID && arg) {
526+
rk805_pmx_gpio_set_direction(pctldev, NULL, pin, true);
527+
break;
528+
}
529+
fallthrough;
396530
default:
397531
dev_err(pci->dev, "Properties not supported\n");
398532
return -ENOTSUPP;
@@ -448,6 +582,18 @@ static int rk805_pinctrl_probe(struct platform_device *pdev)
448582
pci->pin_cfg = rk805_gpio_cfgs;
449583
pci->gpio_chip.ngpio = ARRAY_SIZE(rk805_gpio_cfgs);
450584
break;
585+
case RK806_ID:
586+
pci->pins = rk806_pins_desc;
587+
pci->num_pins = ARRAY_SIZE(rk806_pins_desc);
588+
pci->functions = rk806_pin_functions;
589+
pci->num_functions = ARRAY_SIZE(rk806_pin_functions);
590+
pci->groups = rk806_pin_groups;
591+
pci->num_pin_groups = ARRAY_SIZE(rk806_pin_groups);
592+
pci->pinctrl_desc.pins = rk806_pins_desc;
593+
pci->pinctrl_desc.npins = ARRAY_SIZE(rk806_pins_desc);
594+
pci->pin_cfg = rk806_gpio_cfgs;
595+
pci->gpio_chip.ngpio = ARRAY_SIZE(rk806_gpio_cfgs);
596+
break;
451597
default:
452598
dev_err(&pdev->dev, "unsupported RK805 ID %lu\n",
453599
pci->rk808->variant);
@@ -488,5 +634,6 @@ static struct platform_driver rk805_pinctrl_driver = {
488634
module_platform_driver(rk805_pinctrl_driver);
489635

490636
MODULE_DESCRIPTION("RK805 pin control and GPIO driver");
637+
MODULE_AUTHOR("Xu Shengfei <xsf@rock-chips.com>");
491638
MODULE_AUTHOR("Joseph Chen <chenjh@rock-chips.com>");
492639
MODULE_LICENSE("GPL v2");

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