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SFxingyuwuConchuOD
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riscv: dts: starfive: Add the nodes and pins of I2Srx/I2Stx0/I2Stx1
Add I2Srx/I2Stx0/I2Stx1 nodes and pins configuration for the StarFive JH7110 SoC. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Reviewed-by: Walker Chen <walker.chen@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi

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Original file line numberDiff line numberDiff line change
@@ -203,6 +203,24 @@
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status = "okay";
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};
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&i2srx {
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pinctrl-names = "default";
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pinctrl-0 = <&i2srx_pins>;
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status = "okay";
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};
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&i2stx0 {
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pinctrl-names = "default";
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pinctrl-0 = <&mclk_ext_pins>;
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status = "okay";
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};
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&i2stx1 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2stx1_pins>;
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status = "okay";
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};
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206224
&mmc0 {
207225
max-frequency = <100000000>;
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bus-width = <8>;
@@ -337,6 +355,46 @@
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};
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};
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i2srx_pins: i2srx-0 {
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clk-sd-pins {
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pinmux = <GPIOMUX(38, GPOUT_LOW,
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GPOEN_DISABLE,
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GPI_SYS_I2SRX_BCLK)>,
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<GPIOMUX(63, GPOUT_LOW,
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GPOEN_DISABLE,
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GPI_SYS_I2SRX_LRCK)>,
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<GPIOMUX(38, GPOUT_LOW,
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GPOEN_DISABLE,
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GPI_SYS_I2STX1_BCLK)>,
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<GPIOMUX(63, GPOUT_LOW,
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GPOEN_DISABLE,
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GPI_SYS_I2STX1_LRCK)>,
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<GPIOMUX(61, GPOUT_LOW,
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GPOEN_DISABLE,
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GPI_SYS_I2SRX_SDIN0)>;
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input-enable;
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};
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};
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i2stx1_pins: i2stx1-0 {
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sd-pins {
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pinmux = <GPIOMUX(44, GPOUT_SYS_I2STX1_SDO0,
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GPOEN_ENABLE,
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GPI_NONE)>;
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bias-disable;
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input-disable;
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};
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};
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mclk_ext_pins: mclk-ext-0 {
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mclk-ext-pins {
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pinmux = <GPIOMUX(4, GPOUT_LOW,
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GPOEN_DISABLE,
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GPI_SYS_MCLK_EXT)>;
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input-enable;
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};
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};
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mmc0_pins: mmc0-0 {
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rst-pins {
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pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,

arch/riscv/boot/dts/starfive/jh7110.dtsi

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Original file line numberDiff line numberDiff line change
@@ -512,6 +512,30 @@
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status = "disabled";
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};
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i2srx: i2s@100e0000 {
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compatible = "starfive,jh7110-i2srx";
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reg = <0x0 0x100e0000 0x0 0x1000>;
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clocks = <&syscrg JH7110_SYSCLK_I2SRX_BCLK_MST>,
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<&syscrg JH7110_SYSCLK_I2SRX_APB>,
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<&syscrg JH7110_SYSCLK_MCLK>,
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<&syscrg JH7110_SYSCLK_MCLK_INNER>,
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<&mclk_ext>,
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<&syscrg JH7110_SYSCLK_I2SRX_BCLK>,
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<&syscrg JH7110_SYSCLK_I2SRX_LRCK>,
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<&i2srx_bclk_ext>,
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<&i2srx_lrck_ext>;
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clock-names = "i2sclk", "apb", "mclk",
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"mclk_inner", "mclk_ext", "bclk",
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"lrck", "bclk_ext", "lrck_ext";
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resets = <&syscrg JH7110_SYSRST_I2SRX_APB>,
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<&syscrg JH7110_SYSRST_I2SRX_BCLK>;
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dmas = <0>, <&dma 24>;
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dma-names = "tx", "rx";
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starfive,syscon = <&sys_syscon 0x18 0x2>;
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#sound-dai-cells = <0>;
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status = "disabled";
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};
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515539
usb0: usb@10100000 {
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compatible = "starfive,jh7110-usb";
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ranges = <0x0 0x0 0x10100000 0x100000>;
@@ -736,6 +760,47 @@
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status = "disabled";
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};
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i2stx0: i2s@120b0000 {
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compatible = "starfive,jh7110-i2stx0";
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reg = <0x0 0x120b0000 0x0 0x1000>;
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clocks = <&syscrg JH7110_SYSCLK_I2STX0_BCLK_MST>,
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<&syscrg JH7110_SYSCLK_I2STX0_APB>,
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<&syscrg JH7110_SYSCLK_MCLK>,
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<&syscrg JH7110_SYSCLK_MCLK_INNER>,
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<&mclk_ext>;
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clock-names = "i2sclk", "apb", "mclk",
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"mclk_inner","mclk_ext";
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resets = <&syscrg JH7110_SYSRST_I2STX0_APB>,
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<&syscrg JH7110_SYSRST_I2STX0_BCLK>;
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dmas = <&dma 47>;
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dma-names = "tx";
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#sound-dai-cells = <0>;
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status = "disabled";
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};
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i2stx1: i2s@120c0000 {
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compatible = "starfive,jh7110-i2stx1";
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reg = <0x0 0x120c0000 0x0 0x1000>;
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clocks = <&syscrg JH7110_SYSCLK_I2STX1_BCLK_MST>,
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<&syscrg JH7110_SYSCLK_I2STX1_APB>,
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<&syscrg JH7110_SYSCLK_MCLK>,
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<&syscrg JH7110_SYSCLK_MCLK_INNER>,
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<&mclk_ext>,
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<&syscrg JH7110_SYSCLK_I2STX1_BCLK>,
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<&syscrg JH7110_SYSCLK_I2STX1_LRCK>,
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<&i2stx_bclk_ext>,
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<&i2stx_lrck_ext>;
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clock-names = "i2sclk", "apb", "mclk",
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"mclk_inner", "mclk_ext", "bclk",
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"lrck", "bclk_ext", "lrck_ext";
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resets = <&syscrg JH7110_SYSRST_I2STX1_APB>,
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<&syscrg JH7110_SYSRST_I2STX1_BCLK>;
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dmas = <&dma 48>;
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dma-names = "tx";
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#sound-dai-cells = <0>;
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status = "disabled";
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};
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739804
sfctemp: temperature-sensor@120e0000 {
740805
compatible = "starfive,jh7110-temp";
741806
reg = <0x0 0x120e0000 0x0 0x10000>;

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