Skip to content

Commit 93287e2

Browse files
torvaldstorvalds
committed
Merge tag 'irq-core-2022-03-21' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull interrupt updates from Thomas Gleixner: "Core code: - Provide generic_handle_irq_safe() which can be invoked from any context (hard interrupt or threaded). This allows to remove ugly workarounds in drivers all over the place. - Use generic_handle_irq_safe() in the affected drivers. - The usual cleanups and improvements. Interrupt chip drivers: - Support for new interrupt chips or not yet supported variants: STM32MP14, Meson GPIO, Apple M1 PMU, Apple M1 AICv2, Qualcomm MPM - Convert the Xilinx driver to generic interrupt domains - Cleanup the irq_chip::name handling - The usual cleanups and improvements all over the place" * tag 'irq-core-2022-03-21' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (52 commits) irqchip: Add Qualcomm MPM controller driver dt-bindings: interrupt-controller: Add Qualcomm MPM support irqchip/apple-aic: Add support for AICv2 irqchip/apple-aic: Support multiple dies irqchip/apple-aic: Dynamically compute register offsets irqchip/apple-aic: Switch to irq_domain_create_tree and sparse hwirqs irqchip/apple-aic: Add Fast IPI support dt-bindings: interrupt-controller: apple,aic2: New binding for AICv2 PCI: apple: Change MSI handling to handle 4-cell AIC fwspec form irqchip/apple-aic: Fix cpumask allocation for FIQs irqchip/meson-gpio: Add support for meson s4 SoCs irqchip/meson-gpio: add select trigger type callback irqchip/meson-gpio: support more than 8 channels gpio irq dt-bindings: interrupt-controller: New binding for Meson-S4 SoCs irqchip/xilinx: Switch to GENERIC_IRQ_MULTI_HANDLER staging: greybus: gpio: Use generic_handle_irq_safe(). net: usb: lan78xx: Use generic_handle_irq_safe(). mfd: ezx-pcap: Use generic_handle_irq_safe(). misc: hi6421-spmi-pmic: Use generic_handle_irq_safe(). irqchip/sifive-plic: Disable S-mode IRQs if running in M-mode ...
2 parents 84c2e17 + 411472a commit 93287e2

48 files changed

Lines changed: 1510 additions & 449 deletions

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

‎Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -18,6 +18,7 @@ Required properties:
1818
"amlogic,meson-g12a-gpio-intc" for G12A SoCs (S905D2, S905X2, S905Y2)
1919
"amlogic,meson-sm1-gpio-intc" for SM1 SoCs (S905D3, S905X3, S905Y3)
2020
"amlogic,meson-a1-gpio-intc" for A1 SoCs (A113L)
21+
"amlogic,meson-s4-gpio-intc" for S4 SoCs (S802X2, S905Y4, S805X2G, S905W2)
2122
- reg : Specifies base physical address and size of the registers.
2223
- interrupt-controller : Identifies the node as an interrupt controller.
2324
- #interrupt-cells : Specifies the number of cells needed to encode an

‎Documentation/devicetree/bindings/interrupt-controller/apple,aic2.yaml‎

Lines changed: 98 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,98 @@
1+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/interrupt-controller/apple,aic2.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: Apple Interrupt Controller 2
8+
9+
maintainers:
10+
- Hector Martin <marcan@marcan.st>
11+
12+
description: |
13+
The Apple Interrupt Controller 2 is a simple interrupt controller present on
14+
Apple ARM SoC platforms starting with t600x (M1 Pro and Max).
15+
16+
It provides the following features:
17+
18+
- Level-triggered hardware IRQs wired to SoC blocks
19+
- Single mask bit per IRQ
20+
- Automatic masking on event delivery (auto-ack)
21+
- Software triggering (ORed with hw line)
22+
- Automatic prioritization (single event/ack register per CPU, lower IRQs =
23+
higher priority)
24+
- Automatic masking on ack
25+
- Support for multiple dies
26+
27+
This device also represents the FIQ interrupt sources on platforms using AIC,
28+
which do not go through a discrete interrupt controller. It also handles
29+
FIQ-based Fast IPIs.
30+
31+
properties:
32+
compatible:
33+
items:
34+
- const: apple,t6000-aic
35+
- const: apple,aic2
36+
37+
interrupt-controller: true
38+
39+
'#interrupt-cells':
40+
const: 4
41+
description: |
42+
The 1st cell contains the interrupt type:
43+
- 0: Hardware IRQ
44+
- 1: FIQ
45+
46+
The 2nd cell contains the die ID.
47+
48+
The next cell contains the interrupt number.
49+
- HW IRQs: interrupt number
50+
- FIQs:
51+
- 0: physical HV timer
52+
- 1: virtual HV timer
53+
- 2: physical guest timer
54+
- 3: virtual guest timer
55+
56+
The last cell contains the interrupt flags. This is normally
57+
IRQ_TYPE_LEVEL_HIGH (4).
58+
59+
reg:
60+
items:
61+
- description: Address and size of the main AIC2 registers.
62+
- description: Address and size of the AIC2 Event register.
63+
64+
reg-names:
65+
items:
66+
- const: core
67+
- const: event
68+
69+
power-domains:
70+
maxItems: 1
71+
72+
required:
73+
- compatible
74+
- '#interrupt-cells'
75+
- interrupt-controller
76+
- reg
77+
- reg-names
78+
79+
additionalProperties: false
80+
81+
allOf:
82+
- $ref: /schemas/interrupt-controller.yaml#
83+
84+
examples:
85+
- |
86+
soc {
87+
#address-cells = <2>;
88+
#size-cells = <2>;
89+
90+
aic: interrupt-controller@28e100000 {
91+
compatible = "apple,t6000-aic", "apple,aic2";
92+
#interrupt-cells = <4>;
93+
interrupt-controller;
94+
reg = <0x2 0x8e100000 0x0 0xc000>,
95+
<0x2 0x8e10c000 0x0 0x4>;
96+
reg-names = "core", "event";
97+
};
98+
};

‎Documentation/devicetree/bindings/interrupt-controller/qcom,mpm.yaml‎

Lines changed: 96 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,96 @@
1+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/interrupt-controller/qcom,mpm.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: Qualcom MPM Interrupt Controller
8+
9+
maintainers:
10+
- Shawn Guo <shawn.guo@linaro.org>
11+
12+
description:
13+
Qualcomm Technologies Inc. SoCs based on the RPM architecture have a
14+
MSM Power Manager (MPM) that is in always-on domain. In addition to managing
15+
resources during sleep, the hardware also has an interrupt controller that
16+
monitors the interrupts when the system is asleep, wakes up the APSS when
17+
one of these interrupts occur and replays it to GIC interrupt controller
18+
after GIC becomes operational.
19+
20+
allOf:
21+
- $ref: /schemas/interrupt-controller.yaml#
22+
23+
properties:
24+
compatible:
25+
items:
26+
- const: qcom,mpm
27+
28+
reg:
29+
maxItems: 1
30+
description:
31+
Specifies the base address and size of vMPM registers in RPM MSG RAM.
32+
33+
interrupts:
34+
maxItems: 1
35+
description:
36+
Specify the IRQ used by RPM to wakeup APSS.
37+
38+
mboxes:
39+
maxItems: 1
40+
description:
41+
Specify the mailbox used to notify RPM for writing vMPM registers.
42+
43+
interrupt-controller: true
44+
45+
'#interrupt-cells':
46+
const: 2
47+
description:
48+
The first cell is the MPM pin number for the interrupt, and the second
49+
is the trigger type.
50+
51+
qcom,mpm-pin-count:
52+
description:
53+
Specify the total MPM pin count that a SoC supports.
54+
$ref: /schemas/types.yaml#/definitions/uint32
55+
56+
qcom,mpm-pin-map:
57+
description:
58+
A set of MPM pin numbers and the corresponding GIC SPIs.
59+
$ref: /schemas/types.yaml#/definitions/uint32-matrix
60+
items:
61+
items:
62+
- description: MPM pin number
63+
- description: GIC SPI number for the MPM pin
64+
65+
required:
66+
- compatible
67+
- reg
68+
- interrupts
69+
- mboxes
70+
- interrupt-controller
71+
- '#interrupt-cells'
72+
- qcom,mpm-pin-count
73+
- qcom,mpm-pin-map
74+
75+
additionalProperties: false
76+
77+
examples:
78+
- |
79+
#include <dt-bindings/interrupt-controller/arm-gic.h>
80+
mpm: interrupt-controller@45f01b8 {
81+
compatible = "qcom,mpm";
82+
interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
83+
reg = <0x45f01b8 0x1000>;
84+
mboxes = <&apcs_glb 1>;
85+
interrupt-controller;
86+
#interrupt-cells = <2>;
87+
interrupt-parent = <&intc>;
88+
qcom,mpm-pin-count = <96>;
89+
qcom,mpm-pin-map = <2 275>,
90+
<5 296>,
91+
<12 422>,
92+
<24 79>,
93+
<86 183>,
94+
<90 260>,
95+
<91 260>;
96+
};

‎Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.yaml‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -20,6 +20,7 @@ properties:
2020
- items:
2121
- enum:
2222
- st,stm32mp1-exti
23+
- st,stm32mp13-exti
2324
- const: syscon
2425

2526
"#interrupt-cells":

‎MAINTAINERS‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1769,7 +1769,7 @@ T: git https://github.com/AsahiLinux/linux.git
17691769
F: Documentation/devicetree/bindings/arm/apple.yaml
17701770
F: Documentation/devicetree/bindings/arm/apple/*
17711771
F: Documentation/devicetree/bindings/i2c/apple,i2c.yaml
1772-
F: Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml
1772+
F: Documentation/devicetree/bindings/interrupt-controller/apple,*
17731773
F: Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml
17741774
F: Documentation/devicetree/bindings/pci/apple,pcie.yaml
17751775
F: Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml

‎arch/microblaze/Kconfig‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -45,6 +45,8 @@ config MICROBLAZE
4545
select SET_FS
4646
select ZONE_DMA
4747
select TRACE_IRQFLAGS_SUPPORT
48+
select GENERIC_IRQ_MULTI_HANDLER
49+
select HANDLE_DOMAIN_IRQ
4850

4951
# Endianness selection
5052
choice

‎arch/microblaze/include/asm/irq.h‎

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,4 @@
1111
struct pt_regs;
1212
extern void do_IRQ(struct pt_regs *regs);
1313

14-
/* should be defined in each interrupt controller driver */
15-
extern unsigned int xintc_get_irq(void);
16-
1714
#endif /* _ASM_MICROBLAZE_IRQ_H */

‎arch/microblaze/kernel/irq.c‎

Lines changed: 1 addition & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -20,27 +20,13 @@
2020
#include <linux/irqchip.h>
2121
#include <linux/of_irq.h>
2222

23-
static u32 concurrent_irq;
24-
2523
void __irq_entry do_IRQ(struct pt_regs *regs)
2624
{
27-
unsigned int irq;
2825
struct pt_regs *old_regs = set_irq_regs(regs);
2926
trace_hardirqs_off();
3027

3128
irq_enter();
32-
irq = xintc_get_irq();
33-
next_irq:
34-
BUG_ON(!irq);
35-
generic_handle_irq(irq);
36-
37-
irq = xintc_get_irq();
38-
if (irq != -1U) {
39-
pr_debug("next irq: %d\n", irq);
40-
++concurrent_irq;
41-
goto next_irq;
42-
}
43-
29+
handle_arch_irq(regs);
4430
irq_exit();
4531
set_irq_regs(old_regs);
4632
trace_hardirqs_on();

‎drivers/gpio/gpio-mt7621.c‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -239,7 +239,6 @@ mediatek_gpio_bank_probe(struct device *dev, int bank)
239239

240240
rg->chip.offset = bank * MTK_BANK_WIDTH;
241241
rg->irq_chip.name = dev_name(dev);
242-
rg->irq_chip.parent_device = dev;
243242
rg->irq_chip.irq_unmask = mediatek_gpio_irq_unmask;
244243
rg->irq_chip.irq_mask = mediatek_gpio_irq_mask;
245244
rg->irq_chip.irq_mask_ack = mediatek_gpio_irq_mask;

‎drivers/gpio/gpio-omap.c‎

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -986,7 +986,8 @@ static void omap_gpio_mod_init(struct gpio_bank *bank)
986986
writel_relaxed(0, base + bank->regs->ctrl);
987987
}
988988

989-
static int omap_gpio_chip_init(struct gpio_bank *bank, struct irq_chip *irqc)
989+
static int omap_gpio_chip_init(struct gpio_bank *bank, struct irq_chip *irqc,
990+
struct device *pm_dev)
990991
{
991992
struct gpio_irq_chip *irq;
992993
static int gpio;
@@ -1052,6 +1053,7 @@ static int omap_gpio_chip_init(struct gpio_bank *bank, struct irq_chip *irqc)
10521053
if (ret)
10531054
return dev_err_probe(bank->chip.parent, ret, "Could not register gpio chip\n");
10541055

1056+
irq_domain_set_pm_device(bank->chip.irq.domain, pm_dev);
10551057
ret = devm_request_irq(bank->chip.parent, bank->irq,
10561058
omap_gpio_irq_handler,
10571059
0, dev_name(bank->chip.parent), bank);
@@ -1402,7 +1404,6 @@ static int omap_gpio_probe(struct platform_device *pdev)
14021404
irqc->irq_bus_sync_unlock = gpio_irq_bus_sync_unlock,
14031405
irqc->name = dev_name(&pdev->dev);
14041406
irqc->flags = IRQCHIP_MASK_ON_SUSPEND;
1405-
irqc->parent_device = dev;
14061407

14071408
bank->irq = platform_get_irq(pdev, 0);
14081409
if (bank->irq <= 0) {
@@ -1466,7 +1467,7 @@ static int omap_gpio_probe(struct platform_device *pdev)
14661467

14671468
omap_gpio_mod_init(bank);
14681469

1469-
ret = omap_gpio_chip_init(bank, irqc);
1470+
ret = omap_gpio_chip_init(bank, irqc, dev);
14701471
if (ret) {
14711472
pm_runtime_put_sync(dev);
14721473
pm_runtime_disable(dev);

0 commit comments

Comments
 (0)