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Gabriel-Fernandzbebarino
Gabriel-Fernandz
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clk: stm32mp13: manage secured clocks
Don't register a clock if this clock is secured. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Link: https://lore.kernel.org/r/20220516070600.7692-8-gabriel.fernandez@foss.st.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
1 parent 5f0d472 commit 93e336c

3 files changed

Lines changed: 164 additions & 14 deletions

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‎drivers/clk/stm32/clk-stm32-core.c‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -46,6 +46,10 @@ static int stm32_rcc_clock_init(struct device *dev,
4646
const struct clock_config *cfg_clock = &data->tab_clocks[n];
4747
struct clk_hw *hw = ERR_PTR(-ENOENT);
4848

49+
if (data->check_security &&
50+
data->check_security(base, cfg_clock))
51+
continue;
52+
4953
if (cfg_clock->func)
5054
hw = (*cfg_clock->func)(dev, data, base, &rlock,
5155
cfg_clock);

‎drivers/clk/stm32/clk-stm32-core.h‎

Lines changed: 13 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -46,6 +46,7 @@ struct stm32_composite_cfg {
4646

4747
struct clock_config {
4848
unsigned long id;
49+
int sec_id;
4950
void *clock_cfg;
5051

5152
struct clk_hw *(*func)(struct device *dev,
@@ -69,6 +70,8 @@ struct stm32_rcc_match_data {
6970
unsigned int maxbinding;
7071
struct clk_stm32_clock_data *clock_data;
7172
u32 clear_offset;
73+
int (*check_security)(void __iomem *base,
74+
const struct clock_config *cfg);
7275
};
7376

7477
int stm32_rcc_reset_init(struct device *dev, const struct of_device_id *match,
@@ -157,25 +160,26 @@ struct clk_hw *clk_stm32_composite_register(struct device *dev,
157160
spinlock_t *lock,
158161
const struct clock_config *cfg);
159162

160-
#define STM32_CLOCK_CFG(_binding, _clk, _struct, _register)\
163+
#define STM32_CLOCK_CFG(_binding, _clk, _sec_id, _struct, _register)\
161164
{\
162165
.id = (_binding),\
166+
.sec_id = (_sec_id),\
163167
.clock_cfg = (_struct) {_clk},\
164168
.func = (_register),\
165169
}
166170

167-
#define STM32_MUX_CFG(_binding, _clk)\
168-
STM32_CLOCK_CFG(_binding, &(_clk), struct clk_stm32_mux *,\
171+
#define STM32_MUX_CFG(_binding, _clk, _sec_id)\
172+
STM32_CLOCK_CFG(_binding, &(_clk), _sec_id, struct clk_stm32_mux *,\
169173
&clk_stm32_mux_register)
170174

171-
#define STM32_GATE_CFG(_binding, _clk)\
172-
STM32_CLOCK_CFG(_binding, &(_clk), struct clk_stm32_gate *,\
175+
#define STM32_GATE_CFG(_binding, _clk, _sec_id)\
176+
STM32_CLOCK_CFG(_binding, &(_clk), _sec_id, struct clk_stm32_gate *,\
173177
&clk_stm32_gate_register)
174178

175-
#define STM32_DIV_CFG(_binding, _clk)\
176-
STM32_CLOCK_CFG(_binding, &(_clk), struct clk_stm32_div *,\
179+
#define STM32_DIV_CFG(_binding, _clk, _sec_id)\
180+
STM32_CLOCK_CFG(_binding, &(_clk), _sec_id, struct clk_stm32_div *,\
177181
&clk_stm32_div_register)
178182

179-
#define STM32_COMPOSITE_CFG(_binding, _clk)\
180-
STM32_CLOCK_CFG(_binding, &(_clk), struct clk_stm32_composite *,\
183+
#define STM32_COMPOSITE_CFG(_binding, _clk, _sec_id)\
184+
STM32_CLOCK_CFG(_binding, &(_clk), _sec_id, struct clk_stm32_composite *,\
181185
&clk_stm32_composite_register)

‎drivers/clk/stm32/clk-stm32mp13.c‎

Lines changed: 147 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -400,6 +400,131 @@ static const struct stm32_mux_cfg stm32mp13_muxes[] = {
400400
CFG_MUX(MUX_SDMMC2, RCC_SDMMC12CKSELR, 3, 3),
401401
};
402402

403+
struct clk_stm32_securiy {
404+
u32 offset;
405+
u8 bit_idx;
406+
unsigned long scmi_id;
407+
};
408+
409+
enum security_clk {
410+
SECF_NONE,
411+
SECF_LPTIM2,
412+
SECF_LPTIM3,
413+
SECF_VREF,
414+
SECF_DCMIPP,
415+
SECF_USBPHY,
416+
SECF_TZC,
417+
SECF_ETZPC,
418+
SECF_IWDG1,
419+
SECF_BSEC,
420+
SECF_STGENC,
421+
SECF_STGENRO,
422+
SECF_USART1,
423+
SECF_USART2,
424+
SECF_SPI4,
425+
SECF_SPI5,
426+
SECF_I2C3,
427+
SECF_I2C4,
428+
SECF_I2C5,
429+
SECF_TIM12,
430+
SECF_TIM13,
431+
SECF_TIM14,
432+
SECF_TIM15,
433+
SECF_TIM16,
434+
SECF_TIM17,
435+
SECF_DMA3,
436+
SECF_DMAMUX2,
437+
SECF_ADC1,
438+
SECF_ADC2,
439+
SECF_USBO,
440+
SECF_TSC,
441+
SECF_PKA,
442+
SECF_SAES,
443+
SECF_CRYP1,
444+
SECF_HASH1,
445+
SECF_RNG1,
446+
SECF_BKPSRAM,
447+
SECF_MCE,
448+
SECF_FMC,
449+
SECF_QSPI,
450+
SECF_SDMMC1,
451+
SECF_SDMMC2,
452+
SECF_ETH1CK,
453+
SECF_ETH1TX,
454+
SECF_ETH1RX,
455+
SECF_ETH1MAC,
456+
SECF_ETH1STP,
457+
SECF_ETH2CK,
458+
SECF_ETH2TX,
459+
SECF_ETH2RX,
460+
SECF_ETH2MAC,
461+
SECF_ETH2STP,
462+
SECF_MCO1,
463+
SECF_MCO2
464+
};
465+
466+
#define SECF(_sec_id, _offset, _bit_idx)[_sec_id] = {\
467+
.offset = _offset,\
468+
.bit_idx = _bit_idx,\
469+
.scmi_id = -1,\
470+
}
471+
472+
static const struct clk_stm32_securiy stm32mp13_security[] = {
473+
SECF(SECF_LPTIM2, RCC_APB3SECSR, RCC_APB3SECSR_LPTIM2SECF),
474+
SECF(SECF_LPTIM3, RCC_APB3SECSR, RCC_APB3SECSR_LPTIM3SECF),
475+
SECF(SECF_VREF, RCC_APB3SECSR, RCC_APB3SECSR_VREFSECF),
476+
SECF(SECF_DCMIPP, RCC_APB4SECSR, RCC_APB4SECSR_DCMIPPSECF),
477+
SECF(SECF_USBPHY, RCC_APB4SECSR, RCC_APB4SECSR_USBPHYSECF),
478+
SECF(SECF_TZC, RCC_APB5SECSR, RCC_APB5SECSR_TZCSECF),
479+
SECF(SECF_ETZPC, RCC_APB5SECSR, RCC_APB5SECSR_ETZPCSECF),
480+
SECF(SECF_IWDG1, RCC_APB5SECSR, RCC_APB5SECSR_IWDG1SECF),
481+
SECF(SECF_BSEC, RCC_APB5SECSR, RCC_APB5SECSR_BSECSECF),
482+
SECF(SECF_STGENC, RCC_APB5SECSR, RCC_APB5SECSR_STGENCSECF),
483+
SECF(SECF_STGENRO, RCC_APB5SECSR, RCC_APB5SECSR_STGENROSECF),
484+
SECF(SECF_USART1, RCC_APB6SECSR, RCC_APB6SECSR_USART1SECF),
485+
SECF(SECF_USART2, RCC_APB6SECSR, RCC_APB6SECSR_USART2SECF),
486+
SECF(SECF_SPI4, RCC_APB6SECSR, RCC_APB6SECSR_SPI4SECF),
487+
SECF(SECF_SPI5, RCC_APB6SECSR, RCC_APB6SECSR_SPI5SECF),
488+
SECF(SECF_I2C3, RCC_APB6SECSR, RCC_APB6SECSR_I2C3SECF),
489+
SECF(SECF_I2C4, RCC_APB6SECSR, RCC_APB6SECSR_I2C4SECF),
490+
SECF(SECF_I2C5, RCC_APB6SECSR, RCC_APB6SECSR_I2C5SECF),
491+
SECF(SECF_TIM12, RCC_APB6SECSR, RCC_APB6SECSR_TIM12SECF),
492+
SECF(SECF_TIM13, RCC_APB6SECSR, RCC_APB6SECSR_TIM13SECF),
493+
SECF(SECF_TIM14, RCC_APB6SECSR, RCC_APB6SECSR_TIM14SECF),
494+
SECF(SECF_TIM15, RCC_APB6SECSR, RCC_APB6SECSR_TIM15SECF),
495+
SECF(SECF_TIM16, RCC_APB6SECSR, RCC_APB6SECSR_TIM16SECF),
496+
SECF(SECF_TIM17, RCC_APB6SECSR, RCC_APB6SECSR_TIM17SECF),
497+
SECF(SECF_DMA3, RCC_AHB2SECSR, RCC_AHB2SECSR_DMA3SECF),
498+
SECF(SECF_DMAMUX2, RCC_AHB2SECSR, RCC_AHB2SECSR_DMAMUX2SECF),
499+
SECF(SECF_ADC1, RCC_AHB2SECSR, RCC_AHB2SECSR_ADC1SECF),
500+
SECF(SECF_ADC2, RCC_AHB2SECSR, RCC_AHB2SECSR_ADC2SECF),
501+
SECF(SECF_USBO, RCC_AHB2SECSR, RCC_AHB2SECSR_USBOSECF),
502+
SECF(SECF_TSC, RCC_AHB4SECSR, RCC_AHB4SECSR_TSCSECF),
503+
SECF(SECF_PKA, RCC_AHB5SECSR, RCC_AHB5SECSR_PKASECF),
504+
SECF(SECF_SAES, RCC_AHB5SECSR, RCC_AHB5SECSR_SAESSECF),
505+
SECF(SECF_CRYP1, RCC_AHB5SECSR, RCC_AHB5SECSR_CRYP1SECF),
506+
SECF(SECF_HASH1, RCC_AHB5SECSR, RCC_AHB5SECSR_HASH1SECF),
507+
SECF(SECF_RNG1, RCC_AHB5SECSR, RCC_AHB5SECSR_RNG1SECF),
508+
SECF(SECF_BKPSRAM, RCC_AHB5SECSR, RCC_AHB5SECSR_BKPSRAMSECF),
509+
SECF(SECF_MCE, RCC_AHB6SECSR, RCC_AHB6SECSR_MCESECF),
510+
SECF(SECF_FMC, RCC_AHB6SECSR, RCC_AHB6SECSR_FMCSECF),
511+
SECF(SECF_QSPI, RCC_AHB6SECSR, RCC_AHB6SECSR_QSPISECF),
512+
SECF(SECF_SDMMC1, RCC_AHB6SECSR, RCC_AHB6SECSR_SDMMC1SECF),
513+
SECF(SECF_SDMMC2, RCC_AHB6SECSR, RCC_AHB6SECSR_SDMMC2SECF),
514+
SECF(SECF_ETH1CK, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH1CKSECF),
515+
SECF(SECF_ETH1TX, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH1TXSECF),
516+
SECF(SECF_ETH1RX, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH1RXSECF),
517+
SECF(SECF_ETH1MAC, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH1MACSECF),
518+
SECF(SECF_ETH1STP, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH1STPSECF),
519+
SECF(SECF_ETH2CK, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH2CKSECF),
520+
SECF(SECF_ETH2TX, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH2TXSECF),
521+
SECF(SECF_ETH2RX, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH2RXSECF),
522+
SECF(SECF_ETH2MAC, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH2MACSECF),
523+
SECF(SECF_ETH2STP, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH2STPSECF),
524+
SECF(SECF_MCO1, RCC_SECCFGR, RCC_SECCFGR_MCO1SEC),
525+
SECF(SECF_MCO2, RCC_SECCFGR, RCC_SECCFGR_MCO2SEC),
526+
};
527+
403528
static const char * const eth12_src[] = {
404529
"pll4_p", "pll3_q"
405530
};
@@ -448,13 +573,29 @@ static struct clk_stm32_composite ck_mco2 = {
448573
};
449574

450575
static const struct clock_config stm32mp13_clock_cfg[] = {
451-
STM32_MUX_CFG(NO_ID, ck_ker_eth1),
452-
STM32_GATE_CFG(ETH1CK_K, eth1ck_k),
453-
STM32_DIV_CFG(ETH1PTP_K, eth1ptp_k),
454-
STM32_COMPOSITE_CFG(CK_MCO1, ck_mco1),
455-
STM32_COMPOSITE_CFG(CK_MCO2, ck_mco2),
576+
STM32_MUX_CFG(NO_ID, ck_ker_eth1, SECF_ETH1CK),
577+
STM32_GATE_CFG(ETH1CK_K, eth1ck_k, SECF_ETH1CK),
578+
STM32_DIV_CFG(ETH1PTP_K, eth1ptp_k, SECF_ETH1CK),
579+
STM32_COMPOSITE_CFG(CK_MCO1, ck_mco1, SECF_MCO1),
580+
STM32_COMPOSITE_CFG(CK_MCO2, ck_mco2, SECF_MCO2),
456581
};
457582

583+
static int stm32mp13_clock_is_provided_by_secure(void __iomem *base,
584+
const struct clock_config *cfg)
585+
{
586+
int sec_id = cfg->sec_id;
587+
588+
if (sec_id != SECF_NONE) {
589+
const struct clk_stm32_securiy *secf;
590+
591+
secf = &stm32mp13_security[sec_id];
592+
593+
return !!(readl(base + secf->offset) & BIT(secf->bit_idx));
594+
}
595+
596+
return 0;
597+
}
598+
458599
static u16 stm32mp13_cpt_gate[GATE_NB];
459600

460601
static struct clk_stm32_clock_data stm32mp13_clock_data = {
@@ -468,6 +609,7 @@ static const struct stm32_rcc_match_data stm32mp13_data = {
468609
.tab_clocks = stm32mp13_clock_cfg,
469610
.num_clocks = ARRAY_SIZE(stm32mp13_clock_cfg),
470611
.clock_data = &stm32mp13_clock_data,
612+
.check_security = &stm32mp13_clock_is_provided_by_secure,
471613
.maxbinding = STM32MP1_LAST_CLK,
472614
.clear_offset = RCC_CLR_OFFSET,
473615
};

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