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Tao ZhangSuzuki K Poulose
Tao Zhang
authored and
Suzuki K Poulose
committed
coresight-tpdm: Add nodes for timestamp request
Add nodes to configure the timestamp request based on input pattern match. Each TPDM that support DSB subunit has maximum of n(n<7) TPR registers to configure value for timestamp request based on input pattern match. Eight 32 bit registers providing DSB interface timestamp request pattern match comparison. And each TPDM that support DSB subunit has maximum of m(m<7) TPMR registers to configure pattern mask for timestamp request. Eight 32 bit registers providing DSB interface timestamp request pattern match mask generation. Add nodes to enable/disable pattern timestamp and set pattern timestamp type. Signed-off-by: Tao Zhang <quic_taozha@quicinc.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/1695882586-10306-12-git-send-email-quic_taozha@quicinc.com
1 parent 5898244 commit 949a4f5

3 files changed

Lines changed: 211 additions & 8 deletions

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‎Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm‎

Lines changed: 39 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -123,4 +123,42 @@ KernelVersion 6.7
123123
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
124124
Description:
125125
(RW) Set/Get the mask of the trigger pattern for the DSB
126-
subunit TPDM.
126+
subunit TPDM.
127+
128+
What: /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/tpr[0:7]
129+
Date: March 2023
130+
KernelVersion 6.7
131+
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
132+
Description:
133+
(RW) Set/Get the value of the pattern for the DSB subunit TPDM.
134+
135+
What: /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/tpmr[0:7]
136+
Date: March 2023
137+
KernelVersion 6.7
138+
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
139+
Description:
140+
(RW) Set/Get the mask of the pattern for the DSB subunit TPDM.
141+
142+
What: /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/enable_ts
143+
Date: March 2023
144+
KernelVersion 6.7
145+
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
146+
Description:
147+
(Write) Set the pattern timestamp of DSB tpdm. Read
148+
the pattern timestamp of DSB tpdm.
149+
150+
Accepts only one of the 2 values - 0 or 1.
151+
0 : Disable DSB pattern timestamp.
152+
1 : Enable DSB pattern timestamp.
153+
154+
What: /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/set_type
155+
Date: March 2023
156+
KernelVersion 6.7
157+
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
158+
Description:
159+
(Write) Set the pattern type of DSB tpdm. Read
160+
the pattern type of DSB tpdm.
161+
162+
Accepts only one of the 2 values - 0 or 1.
163+
0 : Set the DSB pattern type to value.
164+
1 : Set the DSB pattern type to toggle.

‎drivers/hwtracing/coresight/coresight-tpdm.c‎

Lines changed: 148 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -51,6 +51,16 @@ static ssize_t tpdm_simple_dataset_show(struct device *dev,
5151
return -EINVAL;
5252
return sysfs_emit(buf, "0x%x\n",
5353
drvdata->dsb->trig_patt_mask[tpdm_attr->idx]);
54+
case DSB_PATT:
55+
if (tpdm_attr->idx >= TPDM_DSB_MAX_PATT)
56+
return -EINVAL;
57+
return sysfs_emit(buf, "0x%x\n",
58+
drvdata->dsb->patt_val[tpdm_attr->idx]);
59+
case DSB_PATT_MASK:
60+
if (tpdm_attr->idx >= TPDM_DSB_MAX_PATT)
61+
return -EINVAL;
62+
return sysfs_emit(buf, "0x%x\n",
63+
drvdata->dsb->patt_mask[tpdm_attr->idx]);
5464
}
5565
return -EINVAL;
5666
}
@@ -85,6 +95,18 @@ static ssize_t tpdm_simple_dataset_store(struct device *dev,
8595
else
8696
ret = -EINVAL;
8797
break;
98+
case DSB_PATT:
99+
if (tpdm_attr->idx < TPDM_DSB_MAX_PATT)
100+
drvdata->dsb->patt_val[tpdm_attr->idx] = val;
101+
else
102+
ret = -EINVAL;
103+
break;
104+
case DSB_PATT_MASK:
105+
if (tpdm_attr->idx < TPDM_DSB_MAX_PATT)
106+
drvdata->dsb->patt_mask[tpdm_attr->idx] = val;
107+
else
108+
ret = -EINVAL;
109+
break;
88110
default:
89111
ret = -EINVAL;
90112
}
@@ -141,6 +163,36 @@ static void set_dsb_mode(struct tpdm_drvdata *drvdata, u32 *val)
141163
*val &= ~TPDM_DSB_CR_MODE;
142164
}
143165

166+
static void set_dsb_tier(struct tpdm_drvdata *drvdata)
167+
{
168+
u32 val;
169+
170+
val = readl_relaxed(drvdata->base + TPDM_DSB_TIER);
171+
172+
/* Clear all relevant fields */
173+
val &= ~(TPDM_DSB_TIER_PATT_TSENAB | TPDM_DSB_TIER_PATT_TYPE |
174+
TPDM_DSB_TIER_XTRIG_TSENAB);
175+
176+
/* Set pattern timestamp type and enablement */
177+
if (drvdata->dsb->patt_ts) {
178+
val |= TPDM_DSB_TIER_PATT_TSENAB;
179+
if (drvdata->dsb->patt_type)
180+
val |= TPDM_DSB_TIER_PATT_TYPE;
181+
else
182+
val &= ~TPDM_DSB_TIER_PATT_TYPE;
183+
} else {
184+
val &= ~TPDM_DSB_TIER_PATT_TSENAB;
185+
}
186+
187+
/* Set trigger timestamp */
188+
if (drvdata->dsb->trig_ts)
189+
val |= TPDM_DSB_TIER_XTRIG_TSENAB;
190+
else
191+
val &= ~TPDM_DSB_TIER_XTRIG_TSENAB;
192+
193+
writel_relaxed(val, drvdata->base + TPDM_DSB_TIER);
194+
}
195+
144196
static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata)
145197
{
146198
u32 val, i;
@@ -152,18 +204,17 @@ static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata)
152204
writel_relaxed(drvdata->dsb->edge_ctrl_mask[i],
153205
drvdata->base + TPDM_DSB_EDCMR(i));
154206
for (i = 0; i < TPDM_DSB_MAX_PATT; i++) {
207+
writel_relaxed(drvdata->dsb->patt_val[i],
208+
drvdata->base + TPDM_DSB_TPR(i));
209+
writel_relaxed(drvdata->dsb->patt_mask[i],
210+
drvdata->base + TPDM_DSB_TPMR(i));
155211
writel_relaxed(drvdata->dsb->trig_patt[i],
156212
drvdata->base + TPDM_DSB_XPR(i));
157213
writel_relaxed(drvdata->dsb->trig_patt_mask[i],
158214
drvdata->base + TPDM_DSB_XPMR(i));
159215
}
160-
val = readl_relaxed(drvdata->base + TPDM_DSB_TIER);
161-
/* Set trigger timestamp */
162-
if (drvdata->dsb->trig_ts)
163-
val |= TPDM_DSB_TIER_XTRIG_TSENAB;
164-
else
165-
val &= ~TPDM_DSB_TIER_XTRIG_TSENAB;
166-
writel_relaxed(val, drvdata->base + TPDM_DSB_TIER);
216+
217+
set_dsb_tier(drvdata);
167218

168219
val = readl_relaxed(drvdata->base + TPDM_DSB_CR);
169220
/* Set the mode of DSB dataset */
@@ -483,6 +534,67 @@ static ssize_t ctrl_mask_store(struct device *dev,
483534
}
484535
static DEVICE_ATTR_WO(ctrl_mask);
485536

537+
static ssize_t enable_ts_show(struct device *dev,
538+
struct device_attribute *attr,
539+
char *buf)
540+
{
541+
struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
542+
543+
return sysfs_emit(buf, "%u\n",
544+
(unsigned int)drvdata->dsb->patt_ts);
545+
}
546+
547+
/*
548+
* value 1: Enable/Disable DSB pattern timestamp
549+
*/
550+
static ssize_t enable_ts_store(struct device *dev,
551+
struct device_attribute *attr,
552+
const char *buf,
553+
size_t size)
554+
{
555+
struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
556+
unsigned long val;
557+
558+
if ((kstrtoul(buf, 0, &val)) || (val & ~1UL))
559+
return -EINVAL;
560+
561+
spin_lock(&drvdata->spinlock);
562+
drvdata->dsb->patt_ts = !!val;
563+
spin_unlock(&drvdata->spinlock);
564+
return size;
565+
}
566+
static DEVICE_ATTR_RW(enable_ts);
567+
568+
static ssize_t set_type_show(struct device *dev,
569+
struct device_attribute *attr,
570+
char *buf)
571+
{
572+
struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
573+
574+
return sysfs_emit(buf, "%u\n",
575+
(unsigned int)drvdata->dsb->patt_type);
576+
}
577+
578+
/*
579+
* value 1: Set DSB pattern type
580+
*/
581+
static ssize_t set_type_store(struct device *dev,
582+
struct device_attribute *attr,
583+
const char *buf, size_t size)
584+
{
585+
struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
586+
unsigned long val;
587+
588+
if ((kstrtoul(buf, 0, &val)) || (val & ~1UL))
589+
return -EINVAL;
590+
591+
spin_lock(&drvdata->spinlock);
592+
drvdata->dsb->patt_type = val;
593+
spin_unlock(&drvdata->spinlock);
594+
return size;
595+
}
596+
static DEVICE_ATTR_RW(set_type);
597+
486598
static ssize_t dsb_trig_type_show(struct device *dev,
487599
struct device_attribute *attr, char *buf)
488600
{
@@ -605,6 +717,28 @@ static struct attribute *tpdm_dsb_trig_patt_attrs[] = {
605717
NULL,
606718
};
607719

720+
static struct attribute *tpdm_dsb_patt_attrs[] = {
721+
DSB_PATT_ATTR(0),
722+
DSB_PATT_ATTR(1),
723+
DSB_PATT_ATTR(2),
724+
DSB_PATT_ATTR(3),
725+
DSB_PATT_ATTR(4),
726+
DSB_PATT_ATTR(5),
727+
DSB_PATT_ATTR(6),
728+
DSB_PATT_ATTR(7),
729+
DSB_PATT_MASK_ATTR(0),
730+
DSB_PATT_MASK_ATTR(1),
731+
DSB_PATT_MASK_ATTR(2),
732+
DSB_PATT_MASK_ATTR(3),
733+
DSB_PATT_MASK_ATTR(4),
734+
DSB_PATT_MASK_ATTR(5),
735+
DSB_PATT_MASK_ATTR(6),
736+
DSB_PATT_MASK_ATTR(7),
737+
&dev_attr_enable_ts.attr,
738+
&dev_attr_set_type.attr,
739+
NULL,
740+
};
741+
608742
static struct attribute *tpdm_dsb_attrs[] = {
609743
&dev_attr_dsb_mode.attr,
610744
&dev_attr_dsb_trig_ts.attr,
@@ -629,11 +763,18 @@ static struct attribute_group tpdm_dsb_trig_patt_grp = {
629763
.name = "dsb_trig_patt",
630764
};
631765

766+
static struct attribute_group tpdm_dsb_patt_grp = {
767+
.attrs = tpdm_dsb_patt_attrs,
768+
.is_visible = tpdm_dsb_is_visible,
769+
.name = "dsb_patt",
770+
};
771+
632772
static const struct attribute_group *tpdm_attr_grps[] = {
633773
&tpdm_attr_grp,
634774
&tpdm_dsb_attr_grp,
635775
&tpdm_dsb_edge_grp,
636776
&tpdm_dsb_trig_patt_grp,
777+
&tpdm_dsb_patt_grp,
637778
NULL,
638779
};
639780

‎drivers/hwtracing/coresight/coresight-tpdm.h‎

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -12,6 +12,8 @@
1212
/* DSB Subunit Registers */
1313
#define TPDM_DSB_CR (0x780)
1414
#define TPDM_DSB_TIER (0x784)
15+
#define TPDM_DSB_TPR(n) (0x788 + (n * 4))
16+
#define TPDM_DSB_TPMR(n) (0x7A8 + (n * 4))
1517
#define TPDM_DSB_XPR(n) (0x7C8 + (n * 4))
1618
#define TPDM_DSB_XPMR(n) (0x7E8 + (n * 4))
1719
#define TPDM_DSB_EDCR(n) (0x808 + (n * 4))
@@ -28,8 +30,12 @@
2830
/* Data bits for DSB test mode */
2931
#define TPDM_DSB_CR_TEST_MODE GENMASK(10, 9)
3032

33+
/* Enable bit for DSB subunit pattern timestamp */
34+
#define TPDM_DSB_TIER_PATT_TSENAB BIT(0)
3135
/* Enable bit for DSB subunit trigger timestamp */
3236
#define TPDM_DSB_TIER_XTRIG_TSENAB BIT(1)
37+
/* Bit for DSB subunit pattern type */
38+
#define TPDM_DSB_TIER_PATT_TYPE BIT(2)
3339

3440
/* DSB programming modes */
3541
/* DSB mode bits mask */
@@ -120,14 +126,26 @@
120126
tpdm_simple_dataset_rw(xpmr##nr, \
121127
DSB_TRIG_PATT_MASK, nr)
122128

129+
#define DSB_PATT_ATTR(nr) \
130+
tpdm_simple_dataset_rw(tpr##nr, \
131+
DSB_PATT, nr)
132+
133+
#define DSB_PATT_MASK_ATTR(nr) \
134+
tpdm_simple_dataset_rw(tpmr##nr, \
135+
DSB_PATT_MASK, nr)
136+
123137
/**
124138
* struct dsb_dataset - specifics associated to dsb dataset
125139
* @mode: DSB programming mode
126140
* @edge_ctrl_idx Index number of the edge control
127141
* @edge_ctrl: Save value for edge control
128142
* @edge_ctrl_mask: Save value for edge control mask
143+
* @patt_val: Save value for pattern
144+
* @patt_mask: Save value for pattern mask
129145
* @trig_patt: Save value for trigger pattern
130146
* @trig_patt_mask: Save value for trigger pattern mask
147+
* @patt_ts: Enable/Disable pattern timestamp
148+
* @patt_type: Set pattern type
131149
* @trig_ts: Enable/Disable trigger timestamp.
132150
* @trig_type: Enable/Disable trigger type.
133151
*/
@@ -136,8 +154,12 @@ struct dsb_dataset {
136154
u32 edge_ctrl_idx;
137155
u32 edge_ctrl[TPDM_DSB_MAX_EDCR];
138156
u32 edge_ctrl_mask[TPDM_DSB_MAX_EDCMR];
157+
u32 patt_val[TPDM_DSB_MAX_PATT];
158+
u32 patt_mask[TPDM_DSB_MAX_PATT];
139159
u32 trig_patt[TPDM_DSB_MAX_PATT];
140160
u32 trig_patt_mask[TPDM_DSB_MAX_PATT];
161+
bool patt_ts;
162+
bool patt_type;
141163
bool trig_ts;
142164
bool trig_type;
143165
};
@@ -169,6 +191,8 @@ enum dataset_mem {
169191
DSB_EDGE_CTRL_MASK,
170192
DSB_TRIG_PATT,
171193
DSB_TRIG_PATT_MASK,
194+
DSB_PATT,
195+
DSB_PATT_MASK,
172196
};
173197

174198
/**

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