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bjorn-helgaasbjorn-helgaas
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Merge branch 'pci/ctrl/dwc-edma'
- Remove unused struct dw_edma_chip.irq (Frank Li) - Move eDMA private data from struct dw_edma to struct dw_edma_chip (Frank Li) - Convert "struct dw_edma_region rg_region" to "void __iomem *reg_base" since only the virtual address (not physical address or size) is used (Frank Li) - Rename "*_ch_cnt" to "ll_*_cnt" to reflect actual usage (Frank Li) - Drop dma_slave_config.direction field usage (Serge Semin) - Fix eDMA Rd/Wr-channels and DMA-direction semantics (Serge Semin) - Add chip-specific DW_EDMA_CHIP_LOCAL flag to indicate that local eDMA doesn't require generating MSIs to remote (Frank Li) - Enable DMA tests for endpoints that support it (Frank Li) * pci/ctrl/dwc-edma: PCI: endpoint: Enable DMA tests for endpoints with DMA capabilities dmaengine: dw-edma: Add support for chip-specific flags dmaengine: dw-edma: Fix eDMA Rd/Wr-channels and DMA-direction semantics dmaengine: dw-edma: Drop dma_slave_config.direction field usage dmaengine: dw-edma: Rename wr(rd)_ch_cnt to ll_wr(rd)_cnt in struct dw_edma_chip dmaengine: dw-edma: Change rg_region to reg_base in struct dw_edma_chip dmaengine: dw-edma: Detach the private data and chip info structures dmaengine: dw-edma: Remove unused irq field in struct dw_edma_chip
2 parents 964db79 + 8353813 commit 94d1331

9 files changed

Lines changed: 322 additions & 181 deletions

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‎drivers/dma/dw-edma/dw-edma-core.c‎

Lines changed: 84 additions & 57 deletions
Original file line numberDiff line numberDiff line change
@@ -64,8 +64,8 @@ static struct dw_edma_burst *dw_edma_alloc_burst(struct dw_edma_chunk *chunk)
6464

6565
static struct dw_edma_chunk *dw_edma_alloc_chunk(struct dw_edma_desc *desc)
6666
{
67+
struct dw_edma_chip *chip = desc->chan->dw->chip;
6768
struct dw_edma_chan *chan = desc->chan;
68-
struct dw_edma *dw = chan->chip->dw;
6969
struct dw_edma_chunk *chunk;
7070

7171
chunk = kzalloc(sizeof(*chunk), GFP_NOWAIT);
@@ -82,11 +82,11 @@ static struct dw_edma_chunk *dw_edma_alloc_chunk(struct dw_edma_desc *desc)
8282
*/
8383
chunk->cb = !(desc->chunks_alloc % 2);
8484
if (chan->dir == EDMA_DIR_WRITE) {
85-
chunk->ll_region.paddr = dw->ll_region_wr[chan->id].paddr;
86-
chunk->ll_region.vaddr = dw->ll_region_wr[chan->id].vaddr;
85+
chunk->ll_region.paddr = chip->ll_region_wr[chan->id].paddr;
86+
chunk->ll_region.vaddr = chip->ll_region_wr[chan->id].vaddr;
8787
} else {
88-
chunk->ll_region.paddr = dw->ll_region_rd[chan->id].paddr;
89-
chunk->ll_region.vaddr = dw->ll_region_rd[chan->id].vaddr;
88+
chunk->ll_region.paddr = chip->ll_region_rd[chan->id].paddr;
89+
chunk->ll_region.vaddr = chip->ll_region_rd[chan->id].vaddr;
9090
}
9191

9292
if (desc->chunk) {
@@ -339,21 +339,40 @@ dw_edma_device_transfer(struct dw_edma_transfer *xfer)
339339
if (!chan->configured)
340340
return NULL;
341341

342-
switch (chan->config.direction) {
343-
case DMA_DEV_TO_MEM: /* local DMA */
344-
if (dir == DMA_DEV_TO_MEM && chan->dir == EDMA_DIR_READ)
345-
break;
346-
return NULL;
347-
case DMA_MEM_TO_DEV: /* local DMA */
348-
if (dir == DMA_MEM_TO_DEV && chan->dir == EDMA_DIR_WRITE)
349-
break;
350-
return NULL;
351-
default: /* remote DMA */
352-
if (dir == DMA_MEM_TO_DEV && chan->dir == EDMA_DIR_READ)
353-
break;
354-
if (dir == DMA_DEV_TO_MEM && chan->dir == EDMA_DIR_WRITE)
355-
break;
356-
return NULL;
342+
/*
343+
* Local Root Port/End-point Remote End-point
344+
* +-----------------------+ PCIe bus +----------------------+
345+
* | | +-+ | |
346+
* | DEV_TO_MEM Rx Ch <----+ +---+ Tx Ch DEV_TO_MEM |
347+
* | | | | | |
348+
* | MEM_TO_DEV Tx Ch +----+ +---> Rx Ch MEM_TO_DEV |
349+
* | | +-+ | |
350+
* +-----------------------+ +----------------------+
351+
*
352+
* 1. Normal logic:
353+
* If eDMA is embedded into the DW PCIe RP/EP and controlled from the
354+
* CPU/Application side, the Rx channel (EDMA_DIR_READ) will be used
355+
* for the device read operations (DEV_TO_MEM) and the Tx channel
356+
* (EDMA_DIR_WRITE) - for the write operations (MEM_TO_DEV).
357+
*
358+
* 2. Inverted logic:
359+
* If eDMA is embedded into a Remote PCIe EP and is controlled by the
360+
* MWr/MRd TLPs sent from the CPU's PCIe host controller, the Tx
361+
* channel (EDMA_DIR_WRITE) will be used for the device read operations
362+
* (DEV_TO_MEM) and the Rx channel (EDMA_DIR_READ) - for the write
363+
* operations (MEM_TO_DEV).
364+
*
365+
* It is the client driver responsibility to choose a proper channel
366+
* for the DMA transfers.
367+
*/
368+
if (chan->dw->chip->flags & DW_EDMA_CHIP_LOCAL) {
369+
if ((chan->dir == EDMA_DIR_READ && dir != DMA_DEV_TO_MEM) ||
370+
(chan->dir == EDMA_DIR_WRITE && dir != DMA_MEM_TO_DEV))
371+
return NULL;
372+
} else {
373+
if ((chan->dir == EDMA_DIR_WRITE && dir != DMA_DEV_TO_MEM) ||
374+
(chan->dir == EDMA_DIR_READ && dir != DMA_MEM_TO_DEV))
375+
return NULL;
357376
}
358377

359378
if (xfer->type == EDMA_XFER_CYCLIC) {
@@ -423,7 +442,7 @@ dw_edma_device_transfer(struct dw_edma_transfer *xfer)
423442
chunk->ll_region.sz += burst->sz;
424443
desc->alloc_sz += burst->sz;
425444

426-
if (chan->dir == EDMA_DIR_WRITE) {
445+
if (dir == DMA_DEV_TO_MEM) {
427446
burst->sar = src_addr;
428447
if (xfer->type == EDMA_XFER_CYCLIC) {
429448
burst->dar = xfer->xfer.cyclic.paddr;
@@ -663,7 +682,7 @@ static int dw_edma_alloc_chan_resources(struct dma_chan *dchan)
663682
if (chan->status != EDMA_ST_IDLE)
664683
return -EBUSY;
665684

666-
pm_runtime_get(chan->chip->dev);
685+
pm_runtime_get(chan->dw->chip->dev);
667686

668687
return 0;
669688
}
@@ -685,15 +704,15 @@ static void dw_edma_free_chan_resources(struct dma_chan *dchan)
685704
cpu_relax();
686705
}
687706

688-
pm_runtime_put(chan->chip->dev);
707+
pm_runtime_put(chan->dw->chip->dev);
689708
}
690709

691-
static int dw_edma_channel_setup(struct dw_edma_chip *chip, bool write,
710+
static int dw_edma_channel_setup(struct dw_edma *dw, bool write,
692711
u32 wr_alloc, u32 rd_alloc)
693712
{
713+
struct dw_edma_chip *chip = dw->chip;
694714
struct dw_edma_region *dt_region;
695715
struct device *dev = chip->dev;
696-
struct dw_edma *dw = chip->dw;
697716
struct dw_edma_chan *chan;
698717
struct dw_edma_irq *irq;
699718
struct dma_device *dma;
@@ -726,17 +745,17 @@ static int dw_edma_channel_setup(struct dw_edma_chip *chip, bool write,
726745

727746
chan->vc.chan.private = dt_region;
728747

729-
chan->chip = chip;
748+
chan->dw = dw;
730749
chan->id = j;
731750
chan->dir = write ? EDMA_DIR_WRITE : EDMA_DIR_READ;
732751
chan->configured = false;
733752
chan->request = EDMA_REQ_NONE;
734753
chan->status = EDMA_ST_IDLE;
735754

736755
if (write)
737-
chan->ll_max = (dw->ll_region_wr[j].sz / EDMA_LL_SZ);
756+
chan->ll_max = (chip->ll_region_wr[j].sz / EDMA_LL_SZ);
738757
else
739-
chan->ll_max = (dw->ll_region_rd[j].sz / EDMA_LL_SZ);
758+
chan->ll_max = (chip->ll_region_rd[j].sz / EDMA_LL_SZ);
740759
chan->ll_max -= 1;
741760

742761
dev_vdbg(dev, "L. List:\tChannel %s[%u] max_cnt=%u\n",
@@ -766,13 +785,13 @@ static int dw_edma_channel_setup(struct dw_edma_chip *chip, bool write,
766785
vchan_init(&chan->vc, dma);
767786

768787
if (write) {
769-
dt_region->paddr = dw->dt_region_wr[j].paddr;
770-
dt_region->vaddr = dw->dt_region_wr[j].vaddr;
771-
dt_region->sz = dw->dt_region_wr[j].sz;
788+
dt_region->paddr = chip->dt_region_wr[j].paddr;
789+
dt_region->vaddr = chip->dt_region_wr[j].vaddr;
790+
dt_region->sz = chip->dt_region_wr[j].sz;
772791
} else {
773-
dt_region->paddr = dw->dt_region_rd[j].paddr;
774-
dt_region->vaddr = dw->dt_region_rd[j].vaddr;
775-
dt_region->sz = dw->dt_region_rd[j].sz;
792+
dt_region->paddr = chip->dt_region_rd[j].paddr;
793+
dt_region->vaddr = chip->dt_region_rd[j].vaddr;
794+
dt_region->sz = chip->dt_region_rd[j].sz;
776795
}
777796

778797
dw_edma_v0_core_device_config(chan);
@@ -826,11 +845,11 @@ static inline void dw_edma_add_irq_mask(u32 *mask, u32 alloc, u16 cnt)
826845
(*mask)++;
827846
}
828847

829-
static int dw_edma_irq_request(struct dw_edma_chip *chip,
848+
static int dw_edma_irq_request(struct dw_edma *dw,
830849
u32 *wr_alloc, u32 *rd_alloc)
831850
{
832-
struct device *dev = chip->dev;
833-
struct dw_edma *dw = chip->dw;
851+
struct dw_edma_chip *chip = dw->chip;
852+
struct device *dev = dw->chip->dev;
834853
u32 wr_mask = 1;
835854
u32 rd_mask = 1;
836855
int i, err = 0;
@@ -839,12 +858,16 @@ static int dw_edma_irq_request(struct dw_edma_chip *chip,
839858

840859
ch_cnt = dw->wr_ch_cnt + dw->rd_ch_cnt;
841860

842-
if (dw->nr_irqs < 1)
861+
if (chip->nr_irqs < 1 || !chip->ops->irq_vector)
843862
return -EINVAL;
844863

845-
if (dw->nr_irqs == 1) {
864+
dw->irq = devm_kcalloc(dev, chip->nr_irqs, sizeof(*dw->irq), GFP_KERNEL);
865+
if (!dw->irq)
866+
return -ENOMEM;
867+
868+
if (chip->nr_irqs == 1) {
846869
/* Common IRQ shared among all channels */
847-
irq = dw->ops->irq_vector(dev, 0);
870+
irq = chip->ops->irq_vector(dev, 0);
848871
err = request_irq(irq, dw_edma_interrupt_common,
849872
IRQF_SHARED, dw->name, &dw->irq[0]);
850873
if (err) {
@@ -854,9 +877,11 @@ static int dw_edma_irq_request(struct dw_edma_chip *chip,
854877

855878
if (irq_get_msi_desc(irq))
856879
get_cached_msi_msg(irq, &dw->irq[0].msi);
880+
881+
dw->nr_irqs = 1;
857882
} else {
858883
/* Distribute IRQs equally among all channels */
859-
int tmp = dw->nr_irqs;
884+
int tmp = chip->nr_irqs;
860885

861886
while (tmp && (*wr_alloc + *rd_alloc) < ch_cnt) {
862887
dw_edma_dec_irq_alloc(&tmp, wr_alloc, dw->wr_ch_cnt);
@@ -867,7 +892,7 @@ static int dw_edma_irq_request(struct dw_edma_chip *chip,
867892
dw_edma_add_irq_mask(&rd_mask, *rd_alloc, dw->rd_ch_cnt);
868893

869894
for (i = 0; i < (*wr_alloc + *rd_alloc); i++) {
870-
irq = dw->ops->irq_vector(dev, i);
895+
irq = chip->ops->irq_vector(dev, i);
871896
err = request_irq(irq,
872897
i < *wr_alloc ?
873898
dw_edma_interrupt_write :
@@ -901,20 +926,22 @@ int dw_edma_probe(struct dw_edma_chip *chip)
901926
return -EINVAL;
902927

903928
dev = chip->dev;
904-
if (!dev)
929+
if (!dev || !chip->ops)
905930
return -EINVAL;
906931

907-
dw = chip->dw;
908-
if (!dw || !dw->irq || !dw->ops || !dw->ops->irq_vector)
909-
return -EINVAL;
932+
dw = devm_kzalloc(dev, sizeof(*dw), GFP_KERNEL);
933+
if (!dw)
934+
return -ENOMEM;
935+
936+
dw->chip = chip;
910937

911938
raw_spin_lock_init(&dw->lock);
912939

913-
dw->wr_ch_cnt = min_t(u16, dw->wr_ch_cnt,
940+
dw->wr_ch_cnt = min_t(u16, chip->ll_wr_cnt,
914941
dw_edma_v0_core_ch_count(dw, EDMA_DIR_WRITE));
915942
dw->wr_ch_cnt = min_t(u16, dw->wr_ch_cnt, EDMA_MAX_WR_CH);
916943

917-
dw->rd_ch_cnt = min_t(u16, dw->rd_ch_cnt,
944+
dw->rd_ch_cnt = min_t(u16, chip->ll_rd_cnt,
918945
dw_edma_v0_core_ch_count(dw, EDMA_DIR_READ));
919946
dw->rd_ch_cnt = min_t(u16, dw->rd_ch_cnt, EDMA_MAX_RD_CH);
920947

@@ -936,33 +963,33 @@ int dw_edma_probe(struct dw_edma_chip *chip)
936963
dw_edma_v0_core_off(dw);
937964

938965
/* Request IRQs */
939-
err = dw_edma_irq_request(chip, &wr_alloc, &rd_alloc);
966+
err = dw_edma_irq_request(dw, &wr_alloc, &rd_alloc);
940967
if (err)
941968
return err;
942969

943970
/* Setup write channels */
944-
err = dw_edma_channel_setup(chip, true, wr_alloc, rd_alloc);
971+
err = dw_edma_channel_setup(dw, true, wr_alloc, rd_alloc);
945972
if (err)
946973
goto err_irq_free;
947974

948975
/* Setup read channels */
949-
err = dw_edma_channel_setup(chip, false, wr_alloc, rd_alloc);
976+
err = dw_edma_channel_setup(dw, false, wr_alloc, rd_alloc);
950977
if (err)
951978
goto err_irq_free;
952979

953980
/* Power management */
954981
pm_runtime_enable(dev);
955982

956983
/* Turn debugfs on */
957-
dw_edma_v0_core_debugfs_on(chip);
984+
dw_edma_v0_core_debugfs_on(dw);
985+
986+
chip->dw = dw;
958987

959988
return 0;
960989

961990
err_irq_free:
962991
for (i = (dw->nr_irqs - 1); i >= 0; i--)
963-
free_irq(dw->ops->irq_vector(dev, i), &dw->irq[i]);
964-
965-
dw->nr_irqs = 0;
992+
free_irq(chip->ops->irq_vector(dev, i), &dw->irq[i]);
966993

967994
return err;
968995
}
@@ -980,7 +1007,7 @@ int dw_edma_remove(struct dw_edma_chip *chip)
9801007

9811008
/* Free irqs */
9821009
for (i = (dw->nr_irqs - 1); i >= 0; i--)
983-
free_irq(dw->ops->irq_vector(dev, i), &dw->irq[i]);
1010+
free_irq(chip->ops->irq_vector(dev, i), &dw->irq[i]);
9841011

9851012
/* Power management */
9861013
pm_runtime_disable(dev);
@@ -1001,7 +1028,7 @@ int dw_edma_remove(struct dw_edma_chip *chip)
10011028
}
10021029

10031030
/* Turn debugfs off */
1004-
dw_edma_v0_core_debugfs_off(chip);
1031+
dw_edma_v0_core_debugfs_off(dw);
10051032

10061033
return 0;
10071034
}

‎drivers/dma/dw-edma/dw-edma-core.h‎

Lines changed: 3 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -15,20 +15,12 @@
1515
#include "../virt-dma.h"
1616

1717
#define EDMA_LL_SZ 24
18-
#define EDMA_MAX_WR_CH 8
19-
#define EDMA_MAX_RD_CH 8
2018

2119
enum dw_edma_dir {
2220
EDMA_DIR_WRITE = 0,
2321
EDMA_DIR_READ
2422
};
2523

26-
enum dw_edma_map_format {
27-
EDMA_MF_EDMA_LEGACY = 0x0,
28-
EDMA_MF_EDMA_UNROLL = 0x1,
29-
EDMA_MF_HDMA_COMPAT = 0x5
30-
};
31-
3224
enum dw_edma_request {
3325
EDMA_REQ_NONE = 0,
3426
EDMA_REQ_STOP,
@@ -57,12 +49,6 @@ struct dw_edma_burst {
5749
u32 sz;
5850
};
5951

60-
struct dw_edma_region {
61-
phys_addr_t paddr;
62-
void __iomem *vaddr;
63-
size_t sz;
64-
};
65-
6652
struct dw_edma_chunk {
6753
struct list_head list;
6854
struct dw_edma_chan *chan;
@@ -87,7 +73,7 @@ struct dw_edma_desc {
8773

8874
struct dw_edma_chan {
8975
struct virt_dma_chan vc;
90-
struct dw_edma_chip *chip;
76+
struct dw_edma *dw;
9177
int id;
9278
enum dw_edma_dir dir;
9379

@@ -109,10 +95,6 @@ struct dw_edma_irq {
10995
struct dw_edma *dw;
11096
};
11197

112-
struct dw_edma_core_ops {
113-
int (*irq_vector)(struct device *dev, unsigned int nr);
114-
};
115-
11698
struct dw_edma {
11799
char name[20];
118100

@@ -122,21 +104,14 @@ struct dw_edma {
122104
struct dma_device rd_edma;
123105
u16 rd_ch_cnt;
124106

125-
struct dw_edma_region rg_region; /* Registers */
126-
struct dw_edma_region ll_region_wr[EDMA_MAX_WR_CH];
127-
struct dw_edma_region ll_region_rd[EDMA_MAX_RD_CH];
128-
struct dw_edma_region dt_region_wr[EDMA_MAX_WR_CH];
129-
struct dw_edma_region dt_region_rd[EDMA_MAX_RD_CH];
130-
131107
struct dw_edma_irq *irq;
132108
int nr_irqs;
133109

134-
enum dw_edma_map_format mf;
135-
136110
struct dw_edma_chan *chan;
137-
const struct dw_edma_core_ops *ops;
138111

139112
raw_spinlock_t lock; /* Only for legacy */
113+
114+
struct dw_edma_chip *chip;
140115
#ifdef CONFIG_DEBUG_FS
141116
struct dentry *debugfs;
142117
#endif /* CONFIG_DEBUG_FS */

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