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Merge tag 'drm-fixes-2024-11-09' of https://gitlab.freedesktop.org/drm/kernel
Pull drm fixes from Dave Airlie: "Weekly fixes, usual leaders in amdgpu and xe, then a panel quirk, and some fixes to imagination and panthor drivers. Seems around the usual level for this time and don't know of any big problems. amdgpu: - Brightness fix - DC vbios parsing fix - ACPI fix - SMU 14.x fix - Power workload profile fix - GC partitioning fix - Debugfs fixes imagination: - Track PVR context per file - Break ref-counting cycle panel-orientation-quirks: - Fix matching Lenovo Yoga Tab 3 X90F panthor: - Lock VM array - Be strict about I/O mapping flags xe: - Fix ccs_mode setting for Xe2 and later - Synchronize ccs_mode setting with client creation - Apply scheduling WA for LNL in additional places as needed - Fix leak and lock handling in error paths of xe_exec ioctl - Fix GGTT allocation leak leading to eventual crash in SR-IOV - Move run_ticks update out of job handling to avoid synchronization with reader" * tag 'drm-fixes-2024-11-09' of https://gitlab.freedesktop.org/drm/kernel: (23 commits) drm/panthor: Be stricter about IO mapping flags drm/panthor: Lock XArray when getting entries for the VM drm: panel-orientation-quirks: Make Lenovo Yoga Tab 3 X90F DMI match less strict drm/xe: Stop accumulating LRC timestamp on job_free drm/xe/pf: Fix potential GGTT allocation leak drm/xe: Drop VM dma-resv lock on xe_sync_in_fence_get failure in exec IOCTL drm/xe: Fix possible exec queue leak in exec IOCTL drm/amdgpu: add missing size check in amdgpu_debugfs_gprwave_read() drm/amdgpu: Adjust debugfs eviction and IB access permissions drm/amdgpu: Adjust debugfs register access permissions drm/amdgpu: Fix DPX valid mode check on GC 9.4.3 drm/amd/pm: correct the workload setting drm/amd/pm: always pick the pptable from IFWI drm/amdgpu: prevent NULL pointer dereference if ATIF is not supported drm/amd/display: parse umc_info or vram_info based on ASIC drm/amd/display: Fix brightness level not retained over reboot drm/xe/guc/tlb: Flush g2h worker in case of tlb timeout drm/xe/ufence: Flush xe ordered_wq in case of ufence timeout drm/xe: Move LNL scheduling WA to xe_device.h drm/xe: Use the filelist from drm for ccs_mode change ...
2 parents 50643bb + 1a6bbc4 commit 952a33d

38 files changed

Lines changed: 257 additions & 155 deletions

‎drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -172,8 +172,8 @@ static union acpi_object *amdgpu_atif_call(struct amdgpu_atif *atif,
172172
&buffer);
173173
obj = (union acpi_object *)buffer.pointer;
174174

175-
/* Fail if calling the method fails and ATIF is supported */
176-
if (ACPI_FAILURE(status) && status != AE_NOT_FOUND) {
175+
/* Fail if calling the method fails */
176+
if (ACPI_FAILURE(status)) {
177177
DRM_DEBUG_DRIVER("failed to evaluate ATIF got %s\n",
178178
acpi_format_exception(status));
179179
kfree(obj);

‎drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -402,7 +402,7 @@ static ssize_t amdgpu_debugfs_gprwave_read(struct file *f, char __user *buf, siz
402402
int r;
403403
uint32_t *data, x;
404404

405-
if (size & 0x3 || *pos & 0x3)
405+
if (size > 4096 || size & 0x3 || *pos & 0x3)
406406
return -EINVAL;
407407

408408
r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
@@ -1648,7 +1648,7 @@ int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
16481648

16491649
for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
16501650
ent = debugfs_create_file(debugfs_regs_names[i],
1651-
S_IFREG | 0444, root,
1651+
S_IFREG | 0400, root,
16521652
adev, debugfs_regs[i]);
16531653
if (!i && !IS_ERR_OR_NULL(ent))
16541654
i_size_write(ent->d_inode, adev->rmmio_size);
@@ -2100,11 +2100,11 @@ int amdgpu_debugfs_init(struct amdgpu_device *adev)
21002100
amdgpu_securedisplay_debugfs_init(adev);
21012101
amdgpu_fw_attestation_debugfs_init(adev);
21022102

2103-
debugfs_create_file("amdgpu_evict_vram", 0444, root, adev,
2103+
debugfs_create_file("amdgpu_evict_vram", 0400, root, adev,
21042104
&amdgpu_evict_vram_fops);
2105-
debugfs_create_file("amdgpu_evict_gtt", 0444, root, adev,
2105+
debugfs_create_file("amdgpu_evict_gtt", 0400, root, adev,
21062106
&amdgpu_evict_gtt_fops);
2107-
debugfs_create_file("amdgpu_test_ib", 0444, root, adev,
2107+
debugfs_create_file("amdgpu_test_ib", 0400, root, adev,
21082108
&amdgpu_debugfs_test_ib_fops);
21092109
debugfs_create_file("amdgpu_vm_info", 0444, root, adev,
21102110
&amdgpu_debugfs_vm_info_fops);

‎drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -482,7 +482,7 @@ static bool __aqua_vanjaram_is_valid_mode(struct amdgpu_xcp_mgr *xcp_mgr,
482482
case AMDGPU_SPX_PARTITION_MODE:
483483
return adev->gmc.num_mem_partitions == 1 && num_xcc > 0;
484484
case AMDGPU_DPX_PARTITION_MODE:
485-
return adev->gmc.num_mem_partitions != 8 && (num_xcc % 4) == 0;
485+
return adev->gmc.num_mem_partitions <= 2 && (num_xcc % 4) == 0;
486486
case AMDGPU_TPX_PARTITION_MODE:
487487
return (adev->gmc.num_mem_partitions == 1 ||
488488
adev->gmc.num_mem_partitions == 3) &&

‎drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c‎

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -9429,6 +9429,7 @@ static void amdgpu_dm_commit_streams(struct drm_atomic_state *state,
94299429
bool mode_set_reset_required = false;
94309430
u32 i;
94319431
struct dc_commit_streams_params params = {dc_state->streams, dc_state->stream_count};
9432+
bool set_backlight_level = false;
94329433

94339434
/* Disable writeback */
94349435
for_each_old_connector_in_state(state, connector, old_con_state, i) {
@@ -9548,6 +9549,7 @@ static void amdgpu_dm_commit_streams(struct drm_atomic_state *state,
95489549
acrtc->hw_mode = new_crtc_state->mode;
95499550
crtc->hwmode = new_crtc_state->mode;
95509551
mode_set_reset_required = true;
9552+
set_backlight_level = true;
95519553
} else if (modereset_required(new_crtc_state)) {
95529554
drm_dbg_atomic(dev,
95539555
"Atomic commit: RESET. crtc id %d:[%p]\n",
@@ -9599,6 +9601,19 @@ static void amdgpu_dm_commit_streams(struct drm_atomic_state *state,
95999601
acrtc->otg_inst = status->primary_otg_inst;
96009602
}
96019603
}
9604+
9605+
/* During boot up and resume the DC layer will reset the panel brightness
9606+
* to fix a flicker issue.
9607+
* It will cause the dm->actual_brightness is not the current panel brightness
9608+
* level. (the dm->brightness is the correct panel level)
9609+
* So we set the backlight level with dm->brightness value after set mode
9610+
*/
9611+
if (set_backlight_level) {
9612+
for (i = 0; i < dm->num_of_edps; i++) {
9613+
if (dm->backlight_dev[i])
9614+
amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]);
9615+
}
9616+
}
96029617
}
96039618

96049619
static void dm_set_writeback(struct amdgpu_display_manager *dm,

‎drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3127,7 +3127,9 @@ static enum bp_result bios_parser_get_vram_info(
31273127
struct atom_data_revision revision;
31283128

31293129
// vram info moved to umc_info for DCN4x
3130-
if (info && DATA_TABLES(umc_info)) {
3130+
if (dcb->ctx->dce_version >= DCN_VERSION_4_01 &&
3131+
dcb->ctx->dce_version < DCN_VERSION_MAX &&
3132+
info && DATA_TABLES(umc_info)) {
31313133
header = GET_IMAGE(struct atom_common_table_header,
31323134
DATA_TABLES(umc_info));
31333135

‎drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c‎

Lines changed: 35 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -1259,26 +1259,33 @@ static int smu_sw_init(void *handle)
12591259
smu->watermarks_bitmap = 0;
12601260
smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
12611261
smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
1262+
smu->user_dpm_profile.user_workload_mask = 0;
12621263

12631264
atomic_set(&smu->smu_power.power_gate.vcn_gated, 1);
12641265
atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1);
12651266
atomic_set(&smu->smu_power.power_gate.vpe_gated, 1);
12661267
atomic_set(&smu->smu_power.power_gate.umsch_mm_gated, 1);
12671268

1268-
smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0;
1269-
smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1;
1270-
smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2;
1271-
smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3;
1272-
smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4;
1273-
smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5;
1274-
smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6;
1269+
smu->workload_priority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0;
1270+
smu->workload_priority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1;
1271+
smu->workload_priority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2;
1272+
smu->workload_priority[PP_SMC_POWER_PROFILE_VIDEO] = 3;
1273+
smu->workload_priority[PP_SMC_POWER_PROFILE_VR] = 4;
1274+
smu->workload_priority[PP_SMC_POWER_PROFILE_COMPUTE] = 5;
1275+
smu->workload_priority[PP_SMC_POWER_PROFILE_CUSTOM] = 6;
12751276

12761277
if (smu->is_apu ||
1277-
!smu_is_workload_profile_available(smu, PP_SMC_POWER_PROFILE_FULLSCREEN3D))
1278-
smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
1279-
else
1280-
smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D];
1278+
!smu_is_workload_profile_available(smu, PP_SMC_POWER_PROFILE_FULLSCREEN3D)) {
1279+
smu->driver_workload_mask =
1280+
1 << smu->workload_priority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
1281+
} else {
1282+
smu->driver_workload_mask =
1283+
1 << smu->workload_priority[PP_SMC_POWER_PROFILE_FULLSCREEN3D];
1284+
smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
1285+
}
12811286

1287+
smu->workload_mask = smu->driver_workload_mask |
1288+
smu->user_dpm_profile.user_workload_mask;
12821289
smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
12831290
smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
12841291
smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING;
@@ -2348,17 +2355,20 @@ static int smu_switch_power_profile(void *handle,
23482355
return -EINVAL;
23492356

23502357
if (!en) {
2351-
smu->workload_mask &= ~(1 << smu->workload_prority[type]);
2358+
smu->driver_workload_mask &= ~(1 << smu->workload_priority[type]);
23522359
index = fls(smu->workload_mask);
23532360
index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
23542361
workload[0] = smu->workload_setting[index];
23552362
} else {
2356-
smu->workload_mask |= (1 << smu->workload_prority[type]);
2363+
smu->driver_workload_mask |= (1 << smu->workload_priority[type]);
23572364
index = fls(smu->workload_mask);
23582365
index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
23592366
workload[0] = smu->workload_setting[index];
23602367
}
23612368

2369+
smu->workload_mask = smu->driver_workload_mask |
2370+
smu->user_dpm_profile.user_workload_mask;
2371+
23622372
if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL &&
23632373
smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)
23642374
smu_bump_power_profile_mode(smu, workload, 0);
@@ -3049,12 +3059,23 @@ static int smu_set_power_profile_mode(void *handle,
30493059
uint32_t param_size)
30503060
{
30513061
struct smu_context *smu = handle;
3062+
int ret;
30523063

30533064
if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled ||
30543065
!smu->ppt_funcs->set_power_profile_mode)
30553066
return -EOPNOTSUPP;
30563067

3057-
return smu_bump_power_profile_mode(smu, param, param_size);
3068+
if (smu->user_dpm_profile.user_workload_mask &
3069+
(1 << smu->workload_priority[param[param_size]]))
3070+
return 0;
3071+
3072+
smu->user_dpm_profile.user_workload_mask =
3073+
(1 << smu->workload_priority[param[param_size]]);
3074+
smu->workload_mask = smu->user_dpm_profile.user_workload_mask |
3075+
smu->driver_workload_mask;
3076+
ret = smu_bump_power_profile_mode(smu, param, param_size);
3077+
3078+
return ret;
30583079
}
30593080

30603081
static int smu_get_fan_control_mode(void *handle, u32 *fan_mode)

‎drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -240,6 +240,7 @@ struct smu_user_dpm_profile {
240240
/* user clock state information */
241241
uint32_t clk_mask[SMU_CLK_COUNT];
242242
uint32_t clk_dependency;
243+
uint32_t user_workload_mask;
243244
};
244245

245246
#define SMU_TABLE_INIT(tables, table_id, s, a, d) \
@@ -557,7 +558,8 @@ struct smu_context {
557558
bool disable_uclk_switch;
558559

559560
uint32_t workload_mask;
560-
uint32_t workload_prority[WORKLOAD_POLICY_MAX];
561+
uint32_t driver_workload_mask;
562+
uint32_t workload_priority[WORKLOAD_POLICY_MAX];
561563
uint32_t workload_setting[WORKLOAD_POLICY_MAX];
562564
uint32_t power_profile_mode;
563565
uint32_t default_power_profile_mode;

‎drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c‎

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1455,7 +1455,6 @@ static int arcturus_set_power_profile_mode(struct smu_context *smu,
14551455
return -EINVAL;
14561456
}
14571457

1458-
14591458
if ((profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) &&
14601459
(smu->smc_fw_version >= 0x360d00)) {
14611460
if (size != 10)
@@ -1523,14 +1522,14 @@ static int arcturus_set_power_profile_mode(struct smu_context *smu,
15231522

15241523
ret = smu_cmn_send_smc_msg_with_param(smu,
15251524
SMU_MSG_SetWorkloadMask,
1526-
1 << workload_type,
1525+
smu->workload_mask,
15271526
NULL);
15281527
if (ret) {
15291528
dev_err(smu->adev->dev, "Fail to set workload type %d\n", workload_type);
15301529
return ret;
15311530
}
15321531

1533-
smu->power_profile_mode = profile_mode;
1532+
smu_cmn_assign_power_profile(smu);
15341533

15351534
return 0;
15361535
}

‎drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2081,10 +2081,13 @@ static int navi10_set_power_profile_mode(struct smu_context *smu, long *input, u
20812081
smu->power_profile_mode);
20822082
if (workload_type < 0)
20832083
return -EINVAL;
2084+
20842085
ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
2085-
1 << workload_type, NULL);
2086+
smu->workload_mask, NULL);
20862087
if (ret)
20872088
dev_err(smu->adev->dev, "[%s] Failed to set work load mask!", __func__);
2089+
else
2090+
smu_cmn_assign_power_profile(smu);
20882091

20892092
return ret;
20902093
}

‎drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1786,10 +1786,13 @@ static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *
17861786
smu->power_profile_mode);
17871787
if (workload_type < 0)
17881788
return -EINVAL;
1789+
17891790
ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1790-
1 << workload_type, NULL);
1791+
smu->workload_mask, NULL);
17911792
if (ret)
17921793
dev_err(smu->adev->dev, "[%s] Failed to set work load mask!", __func__);
1794+
else
1795+
smu_cmn_assign_power_profile(smu);
17931796

17941797
return ret;
17951798
}

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