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arm64/sysreg: Convert SPE registers to automatic generation
Convert all the SPE register defines to automatic generation. No functional changes. New registers and fields for SPEv1.2 are added with the conversion. Some of the PMBSR MSS field defines are kept as the automatic generation has no way to create multiple names for the same register bits. The meaning of the MSS field depends on other bits. Tested-by: James Clark <james.clark@arm.com> Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Mark Brown <broonie@kernel.org> Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com> Link: https://lore.kernel.org/r/20220825-arm-spe-v8-7-v4-3-327f860daf28@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
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Lines changed: 144 additions & 86 deletions

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‎arch/arm64/include/asm/sysreg.h‎

Lines changed: 5 additions & 86 deletions
Original file line numberDiff line numberDiff line change
@@ -216,99 +216,18 @@
216216
#define SYS_PAR_EL1_FST GENMASK(6, 1)
217217

218218
/*** Statistical Profiling Extension ***/
219-
/* ID registers */
220-
#define SYS_PMSIDR_EL1 sys_reg(3, 0, 9, 9, 7)
221-
#define PMSIDR_EL1_FE_SHIFT 0
222-
#define PMSIDR_EL1_FT_SHIFT 1
223-
#define PMSIDR_EL1_FL_SHIFT 2
224-
#define PMSIDR_EL1_ARCHINST_SHIFT 3
225-
#define PMSIDR_EL1_LDS_SHIFT 4
226-
#define PMSIDR_EL1_ERND_SHIFT 5
227-
#define PMSIDR_EL1_INTERVAL_SHIFT 8
228-
#define PMSIDR_EL1_INTERVAL_MASK GENMASK_ULL(11, 8)
229-
#define PMSIDR_EL1_MAXSIZE_SHIFT 12
230-
#define PMSIDR_EL1_MAXSIZE_MASK GENMASK_ULL(15, 12)
231-
#define PMSIDR_EL1_COUNTSIZE_SHIFT 16
232-
#define PMSIDR_EL1_COUNTSIZE_MASK GENMASK_ULL(19, 16)
233-
234-
#define SYS_PMBIDR_EL1 sys_reg(3, 0, 9, 10, 7)
235-
#define PMBIDR_EL1_ALIGN_SHIFT 0
236-
#define PMBIDR_EL1_ALIGN_MASK 0xfU
237-
#define PMBIDR_EL1_P_SHIFT 4
238-
#define PMBIDR_EL1_F_SHIFT 5
239-
240-
/* Sampling controls */
241-
#define SYS_PMSCR_EL1 sys_reg(3, 0, 9, 9, 0)
242-
#define PMSCR_EL1_E0SPE_SHIFT 0
243-
#define PMSCR_EL1_E1SPE_SHIFT 1
244-
#define PMSCR_EL1_CX_SHIFT 3
245-
#define PMSCR_EL1_PA_SHIFT 4
246-
#define PMSCR_EL1_TS_SHIFT 5
247-
#define PMSCR_EL1_PCT_SHIFT 6
248-
249-
#define SYS_PMSCR_EL2 sys_reg(3, 4, 9, 9, 0)
250-
#define PMSCR_EL2_E0HSPE_SHIFT 0
251-
#define PMSCR_EL2_E2SPE_SHIFT 1
252-
#define PMSCR_EL2_CX_SHIFT 3
253-
#define PMSCR_EL2_PA_SHIFT 4
254-
#define PMSCR_EL2_TS_SHIFT 5
255-
#define PMSCR_EL2_PCT_SHIFT 6
256-
257-
#define SYS_PMSICR_EL1 sys_reg(3, 0, 9, 9, 2)
258-
259-
#define SYS_PMSIRR_EL1 sys_reg(3, 0, 9, 9, 3)
260-
#define PMSIRR_EL1_RND_SHIFT 0
261-
#define PMSIRR_EL1_INTERVAL_SHIFT 8
262-
#define PMSIRR_EL1_INTERVAL_MASK GENMASK_ULL(31, 8)
263-
264-
/* Filtering controls */
265-
#define SYS_PMSNEVFR_EL1 sys_reg(3, 0, 9, 9, 1)
266-
267-
#define SYS_PMSFCR_EL1 sys_reg(3, 0, 9, 9, 4)
268-
#define PMSFCR_EL1_FE_SHIFT 0
269-
#define PMSFCR_EL1_FT_SHIFT 1
270-
#define PMSFCR_EL1_FL_SHIFT 2
271-
#define PMSFCR_EL1_B_SHIFT 16
272-
#define PMSFCR_EL1_LD_SHIFT 17
273-
#define PMSFCR_EL1_ST_SHIFT 18
274-
275-
#define SYS_PMSEVFR_EL1 sys_reg(3, 0, 9, 9, 5)
276219
#define PMSEVFR_EL1_RES0_IMP \
277220
(GENMASK_ULL(47, 32) | GENMASK_ULL(23, 16) | GENMASK_ULL(11, 8) |\
278221
BIT_ULL(6) | BIT_ULL(4) | BIT_ULL(2) | BIT_ULL(0))
279222
#define PMSEVFR_EL1_RES0_V1P1 \
280223
(PMSEVFR_EL1_RES0_IMP & ~(BIT_ULL(18) | BIT_ULL(17) | BIT_ULL(11)))
281224

282-
#define SYS_PMSLATFR_EL1 sys_reg(3, 0, 9, 9, 6)
283-
#define PMSLATFR_EL1_MINLAT_SHIFT 0
284-
285-
/* Buffer controls */
286-
#define SYS_PMBLIMITR_EL1 sys_reg(3, 0, 9, 10, 0)
287-
#define PMBLIMITR_EL1_E_SHIFT 0
288-
#define PMBLIMITR_EL1_FM_SHIFT 1
289-
#define PMBLIMITR_EL1_FM_MASK GENMASK_ULL(2, 1)
290-
#define PMBLIMITR_EL1_FM_STOP_IRQ 0
291-
292-
#define SYS_PMBPTR_EL1 sys_reg(3, 0, 9, 10, 1)
293-
294225
/* Buffer error reporting */
295-
#define SYS_PMBSR_EL1 sys_reg(3, 0, 9, 10, 3)
296-
#define PMBSR_EL1_COLL_SHIFT 16
297-
#define PMBSR_EL1_S_SHIFT 17
298-
#define PMBSR_EL1_EA_SHIFT 18
299-
#define PMBSR_EL1_DL_SHIFT 19
300-
#define PMBSR_EL1_EC_SHIFT 26
301-
#define PMBSR_EL1_EC_MASK GENMASK_ULL(31, 26)
302-
303-
#define PMBSR_EL1_EC_BUF 0x0UL
304-
#define PMBSR_EL1_EC_FAULT_S1 0x24UL
305-
#define PMBSR_EL1_EC_FAULT_S2 0x25UL
306-
307-
#define PMBSR_EL1_FAULT_FSC_SHIFT 0
308-
#define PMBSR_EL1_FAULT_FSC_MASK 0x3fUL
309-
310-
#define PMBSR_EL1_BUF_BSC_SHIFT 0
311-
#define PMBSR_EL1_BUF_BSC_MASK 0x3fUL
226+
#define PMBSR_EL1_FAULT_FSC_SHIFT PMBSR_EL1_MSS_SHIFT
227+
#define PMBSR_EL1_FAULT_FSC_MASK PMBSR_EL1_MSS_MASK
228+
229+
#define PMBSR_EL1_BUF_BSC_SHIFT PMBSR_EL1_MSS_SHIFT
230+
#define PMBSR_EL1_BUF_BSC_MASK PMBSR_EL1_MSS_MASK
312231

313232
#define PMBSR_EL1_BUF_BSC_FULL 0x1UL
314233

‎arch/arm64/tools/sysreg‎

Lines changed: 139 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1618,6 +1618,130 @@ Sysreg FAR_EL1 3 0 6 0 0
16181618
Field 63:0 ADDR
16191619
EndSysreg
16201620

1621+
Sysreg PMSCR_EL1 3 0 9 9 0
1622+
Res0 63:8
1623+
Field 7:6 PCT
1624+
Field 5 TS
1625+
Field 4 PA
1626+
Field 3 CX
1627+
Res0 2
1628+
Field 1 E1SPE
1629+
Field 0 E0SPE
1630+
EndSysreg
1631+
1632+
Sysreg PMSNEVFR_EL1 3 0 9 9 1
1633+
Field 63:0 E
1634+
EndSysreg
1635+
1636+
Sysreg PMSICR_EL1 3 0 9 9 2
1637+
Field 63:56 ECOUNT
1638+
Res0 55:32
1639+
Field 31:0 COUNT
1640+
EndSysreg
1641+
1642+
Sysreg PMSIRR_EL1 3 0 9 9 3
1643+
Res0 63:32
1644+
Field 31:8 INTERVAL
1645+
Res0 7:1
1646+
Field 0 RND
1647+
EndSysreg
1648+
1649+
Sysreg PMSFCR_EL1 3 0 9 9 4
1650+
Res0 63:19
1651+
Field 18 ST
1652+
Field 17 LD
1653+
Field 16 B
1654+
Res0 15:4
1655+
Field 3 FnE
1656+
Field 2 FL
1657+
Field 1 FT
1658+
Field 0 FE
1659+
EndSysreg
1660+
1661+
Sysreg PMSEVFR_EL1 3 0 9 9 5
1662+
Field 63:0 E
1663+
EndSysreg
1664+
1665+
Sysreg PMSLATFR_EL1 3 0 9 9 6
1666+
Res0 63:16
1667+
Field 15:0 MINLAT
1668+
EndSysreg
1669+
1670+
Sysreg PMSIDR_EL1 3 0 9 9 7
1671+
Res0 63:25
1672+
Field 24 PBT
1673+
Field 23:20 FORMAT
1674+
Enum 19:16 COUNTSIZE
1675+
0b0010 12_BIT_SAT
1676+
0b0011 16_BIT_SAT
1677+
EndEnum
1678+
Field 15:12 MAXSIZE
1679+
Enum 11:8 INTERVAL
1680+
0b0000 256
1681+
0b0010 512
1682+
0b0011 768
1683+
0b0100 1024
1684+
0b0101 1536
1685+
0b0110 2048
1686+
0b0111 3072
1687+
0b1000 4096
1688+
EndEnum
1689+
Res0 7
1690+
Field 6 FnE
1691+
Field 5 ERND
1692+
Field 4 LDS
1693+
Field 3 ARCHINST
1694+
Field 2 FL
1695+
Field 1 FT
1696+
Field 0 FE
1697+
EndSysreg
1698+
1699+
Sysreg PMBLIMITR_EL1 3 0 9 10 0
1700+
Field 63:12 LIMIT
1701+
Res0 11:6
1702+
Field 5 PMFZ
1703+
Res0 4:3
1704+
Enum 2:1 FM
1705+
0b00 FILL
1706+
0b10 DISCARD
1707+
EndEnum
1708+
Field 0 E
1709+
EndSysreg
1710+
1711+
Sysreg PMBPTR_EL1 3 0 9 10 1
1712+
Field 63:0 PTR
1713+
EndSysreg
1714+
1715+
Sysreg PMBSR_EL1 3 0 9 10 3
1716+
Res0 63:32
1717+
Enum 31:26 EC
1718+
0b000000 BUF
1719+
0b100100 FAULT_S1
1720+
0b100101 FAULT_S2
1721+
0b011110 FAULT_GPC
1722+
0b011111 IMP_DEF
1723+
EndEnum
1724+
Res0 25:20
1725+
Field 19 DL
1726+
Field 18 EA
1727+
Field 17 S
1728+
Field 16 COLL
1729+
Field 15:0 MSS
1730+
EndSysreg
1731+
1732+
Sysreg PMBIDR_EL1 3 0 9 10 7
1733+
Res0 63:12
1734+
Enum 11:8 EA
1735+
0b0000 NotDescribed
1736+
0b0001 Ignored
1737+
0b0010 SError
1738+
EndEnum
1739+
Res0 7:6
1740+
Field 5 F
1741+
Field 4 P
1742+
Field 3:0 ALIGN
1743+
EndSysreg
1744+
16211745
SysregFields CONTEXTIDR_ELx
16221746
Res0 63:32
16231747
Field 31:0 PROCID
@@ -1772,6 +1896,21 @@ Sysreg FAR_EL2 3 4 6 0 0
17721896
Field 63:0 ADDR
17731897
EndSysreg
17741898

1899+
Sysreg PMSCR_EL2 3 4 9 9 0
1900+
Res0 63:8
1901+
Enum 7:6 PCT
1902+
0b00 VIRT
1903+
0b01 PHYS
1904+
0b11 GUEST
1905+
EndEnum
1906+
Field 5 TS
1907+
Field 4 PA
1908+
Field 3 CX
1909+
Res0 2
1910+
Field 1 E2SPE
1911+
Field 0 E0HSPE
1912+
EndSysreg
1913+
17751914
Sysreg CONTEXTIDR_EL2 3 4 13 0 1
17761915
Fields CONTEXTIDR_ELx
17771916
EndSysreg

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