Skip to content

Commit 95c91e7

Browse files
prabhakarladgeertu
authored andcommitted
arm64: dts: renesas: r9a07g044: Add CSI and CRU nodes
Add CSI and CRU nodes r9a07g044 (RZ/G2L) SoC DTSI. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230322125648.24948-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
1 parent 52a3554 commit 95c91e7

1 file changed

Lines changed: 79 additions & 0 deletions

File tree

arch/arm64/boot/dts/renesas/r9a07g044.dtsi

Lines changed: 79 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -618,6 +618,85 @@
618618
status = "disabled";
619619
};
620620

621+
cru: video@10830000 {
622+
compatible = "renesas,r9a07g044-cru", "renesas,rzg2l-cru";
623+
reg = <0 0x10830000 0 0x400>;
624+
clocks = <&cpg CPG_MOD R9A07G044_CRU_VCLK>,
625+
<&cpg CPG_MOD R9A07G044_CRU_PCLK>,
626+
<&cpg CPG_MOD R9A07G044_CRU_ACLK>;
627+
clock-names = "video", "apb", "axi";
628+
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
629+
<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
630+
<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
631+
interrupt-names = "image_conv", "image_conv_err", "axi_mst_err";
632+
resets = <&cpg R9A07G044_CRU_PRESETN>,
633+
<&cpg R9A07G044_CRU_ARESETN>;
634+
reset-names = "presetn", "aresetn";
635+
power-domains = <&cpg>;
636+
status = "disabled";
637+
638+
ports {
639+
#address-cells = <1>;
640+
#size-cells = <0>;
641+
642+
port@0 {
643+
#address-cells = <1>;
644+
#size-cells = <0>;
645+
646+
reg = <0>;
647+
cruparallel: endpoint@0 {
648+
reg = <0>;
649+
};
650+
};
651+
652+
port@1 {
653+
#address-cells = <1>;
654+
#size-cells = <0>;
655+
656+
reg = <1>;
657+
crucsi2: endpoint@0 {
658+
reg = <0>;
659+
remote-endpoint = <&csi2cru>;
660+
};
661+
};
662+
};
663+
};
664+
665+
csi2: csi2@10830400 {
666+
compatible = "renesas,r9a07g044-csi2", "renesas,rzg2l-csi2";
667+
reg = <0 0x10830400 0 0xfc00>;
668+
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
669+
clocks = <&cpg CPG_MOD R9A07G044_CRU_SYSCLK>,
670+
<&cpg CPG_MOD R9A07G044_CRU_VCLK>,
671+
<&cpg CPG_MOD R9A07G044_CRU_PCLK>;
672+
clock-names = "system", "video", "apb";
673+
resets = <&cpg R9A07G044_CRU_PRESETN>,
674+
<&cpg R9A07G044_CRU_CMN_RSTB>;
675+
reset-names = "presetn", "cmn-rstb";
676+
power-domains = <&cpg>;
677+
status = "disabled";
678+
679+
ports {
680+
#address-cells = <1>;
681+
#size-cells = <0>;
682+
683+
port@0 {
684+
reg = <0>;
685+
};
686+
687+
port@1 {
688+
#address-cells = <1>;
689+
#size-cells = <0>;
690+
reg = <1>;
691+
692+
csi2cru: endpoint@0 {
693+
reg = <0>;
694+
remote-endpoint = <&crucsi2>;
695+
};
696+
};
697+
};
698+
};
699+
621700
cpg: clock-controller@11010000 {
622701
compatible = "renesas,r9a07g044-cpg";
623702
reg = <0 0x11010000 0 0x10000>;

0 commit comments

Comments
 (0)