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32623262 power-domains = <&gcc GCC_PCIE_3_GDSC>;
32633263
3264- phys = <&pcie3_phy>;
3265- phy-names = "pciephy";
3266-
32673264 eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555
32683265 0x5555 0x5555 0x5555 0x5555>;
32693266 eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55 0x55 0x55 0x55 0x55>;
34043401 };
34053402 };
34063403
3407- pcie3_port : pcie@0 {
3404+ pcie3_port0 : pcie@0 {
34083405 device_type = "pci";
34093406 compatible = "pciclass,0604";
34103407 reg = <0x0 0x0 0x0 0x0 0x0>;
34113408 bus-range = <0x01 0xff>;
34123409
3410+ phys = <&pcie3_phy>;
3411+
34133412 #address-cells = <3>;
34143413 #size-cells = <2>;
34153414 ranges;
35383537 power-domains = <&gcc GCC_PCIE_6A_GDSC>;
35393538 required-opps = <&rpmhpd_opp_nom>;
35403539
3541- phys = <&pcie6a_phy>;
3542- phy-names = "pciephy";
3543-
35443540 eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>;
35453541 eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>;
35463542
35473543 status = "disabled";
3544+
3545+ pcie6a_port0: pcie@0 {
3546+ device_type = "pci";
3547+ reg = <0x0 0x0 0x0 0x0 0x0>;
3548+ bus-range = <0x01 0xff>;
3549+
3550+ phys = <&pcie6a_phy>;
3551+
3552+ #address-cells = <3>;
3553+ #size-cells = <2>;
3554+ ranges;
3555+ };
35483556 };
35493557
35503558 pcie6a_phy: phy@1bfc000 {
36703678 power-domains = <&gcc GCC_PCIE_5_GDSC>;
36713679 required-opps = <&rpmhpd_opp_nom>;
36723680
3673- phys = <&pcie5_phy>;
3674- phy-names = "pciephy";
3675-
36763681 eq-presets-8gts = /bits/ 16 <0x5555 0x5555>;
36773682
36783683 status = "disabled";
3684+
3685+ pcie5_port0: pcie@0 {
3686+ device_type = "pci";
3687+ reg = <0x0 0x0 0x0 0x0 0x0>;
3688+ bus-range = <0x01 0xff>;
3689+
3690+ phys = <&pcie5_phy>;
3691+
3692+ #address-cells = <3>;
3693+ #size-cells = <2>;
3694+ ranges;
3695+ };
36793696 };
36803697
36813698 pcie5_phy: phy@1c06000 {
38003817 power-domains = <&gcc GCC_PCIE_4_GDSC>;
38013818 required-opps = <&rpmhpd_opp_nom>;
38023819
3803- phys = <&pcie4_phy>;
3804- phy-names = "pciephy";
3805-
38063820 eq-presets-8gts = /bits/ 16 <0x5555 0x5555>;
38073821
38083822 status = "disabled";
38123826 reg = <0x0 0x0 0x0 0x0 0x0>;
38133827 bus-range = <0x01 0xff>;
38143828
3829+ phys = <&pcie4_phy>;
3830+
38153831 #address-cells = <3>;
38163832 #size-cells = <2>;
38173833 ranges;
Original file line number Diff line number Diff line change 10031003};
10041004
10051005&pcie4 {
1006- perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
1007- wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
1008-
10091006 pinctrl-0 = <&pcie4_default>;
10101007 pinctrl-names = "default";
10111008
10191016 status = "okay";
10201017};
10211018
1022- &pcie5 {
1023- perst-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>;
1024- wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
1019+ &pcie4_port0 {
1020+ reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
1021+ wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
1022+ };
10251023
1024+ &pcie5 {
10261025 vddpe-3v3-supply = <&vreg_wwan>;
10271026
10281027 pinctrl-0 = <&pcie5_default>;
10381037 status = "okay";
10391038};
10401039
1041- &pcie6a {
1042- perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
1043- wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
1040+ &pcie5_port0 {
1041+ reset-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>;
1042+ wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
1043+ };
10441044
1045+ &pcie6a {
10451046 vddpe-3v3-supply = <&vreg_nvme>;
10461047
10471048 pinctrl-names = "default";
10571058 status = "okay";
10581059};
10591060
1061+ &pcie6a_port0 {
1062+ reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
1063+ wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
1064+ };
1065+
10601066&pm8550_gpios {
10611067 rtmr0_default: rtmr0-reset-n-active-state {
10621068 pins = "gpio10";
Original file line number Diff line number Diff line change 11131113};
11141114
11151115&pcie4 {
1116- perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
1117- wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
1118-
11191116 pinctrl-0 = <&pcie4_default>;
11201117 pinctrl-names = "default";
11211118
11291126 status = "okay";
11301127};
11311128
1132- &pcie5 {
1133- perst-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>;
1134- wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
1129+ &pcie4_port0 {
1130+ reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
1131+ wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
1132+ };
11351133
1134+ &pcie5 {
11361135 vddpe-3v3-supply = <&vreg_wwan>;
11371136
11381137 pinctrl-0 = <&pcie5_default>;
11481147 status = "okay";
11491148};
11501149
1151- &pcie6a {
1152- perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
1153- wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
1150+ &pcie5_port0 {
1151+ reset-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>;
1152+ wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
1153+ };
11541154
1155+ &pcie6a {
11551156 vddpe-3v3-supply = <&vreg_nvme>;
11561157
11571158 pinctrl-0 = <&pcie6a_default>;
11671168 status = "okay";
11681169};
11691170
1171+ &pcie6a_port0 {
1172+ reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
1173+ wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
1174+ };
1175+
11701176&pm8550_gpios {
11711177 rtmr0_default: rtmr0-reset-n-active-state {
11721178 pins = "gpio10";
Original file line number Diff line number Diff line change 907907};
908908
909909&pcie4 {
910- perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
911- wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
912-
913910 pinctrl-0 = <&pcie4_default>;
914911 pinctrl-names = "default";
915912
924921};
925922
926923&pcie4_port0 {
924+ reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
925+ wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
926+
927927 wifi@0 {
928928 compatible = "pci17cb,1107";
929929 reg = <0x10000 0x0 0x0 0x0 0x0>;
941941};
942942
943943&pcie6a {
944- perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
945- wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
946-
947944 vddpe-3v3-supply = <&vreg_nvme>;
948945
949946 pinctrl-0 = <&pcie6a_default>;
959956 status = "okay";
960957};
961958
959+ &pcie6a_port0 {
960+ reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
961+ wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
962+ };
963+
962964&pm8550_gpios {
963965 rtmr0_default: rtmr0-reset-n-active-state {
964966 pins = "gpio10";
Original file line number Diff line number Diff line change 8282};
8383
8484&pcie4_port0 {
85+ reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
86+ wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
87+
8588 wifi@0 {
8689 compatible = "pci17cb,1107";
8790 reg = <0x10000 0x0 0x0 0x0 0x0>;
Original file line number Diff line number Diff line change 941941};
942942
943943&pcie4 {
944- perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
945- wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
946-
947944 pinctrl-0 = <&pcie4_default>;
948945 pinctrl-names = "default";
949946
958955};
959956
960957&pcie4_port0 {
958+ reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
959+ wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
960+
961961 wifi@0 {
962962 compatible = "pci17cb,1107";
963963 reg = <0x10000 0x0 0x0 0x0 0x0>;
975975};
976976
977977&pcie6a {
978- perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
979- wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
980-
981978 vddpe-3v3-supply = <&vreg_nvme>;
982979
983980 pinctrl-0 = <&pcie6a_default>;
993990 status = "okay";
994991};
995992
993+ &pcie6a_port0 {
994+ reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
995+ wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
996+ };
997+
996998&pm8550_gpios {
997999 rtmr0_default: rtmr0-reset-n-active-state {
9981000 pins = "gpio10";
Original file line number Diff line number Diff line change 11601160};
11611161
11621162&pcie6a {
1163- perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
1164- wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
1165-
11661163 vddpe-3v3-supply = <&vreg_nvme>;
11671164
11681165 pinctrl-0 = <&pcie6a_default>;
11781175 status = "okay";
11791176};
11801177
1178+ &pcie6a_port0 {
1179+ reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
1180+ wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
1181+ };
1182+
11811183&pm8550_gpios {
11821184 rtmr0_default: rtmr0-reset-n-active-state {
11831185 pins = "gpio10";
Original file line number Diff line number Diff line change 10941094};
10951095
10961096&pcie3 {
1097- perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
1098- wake-gpios = <&tlmm 145 GPIO_ACTIVE_HIGH>;
1099-
11001097 pinctrl-0 = <&pcie3_default>;
11011098 pinctrl-names = "default";
11021099
11121109 status = "okay";
11131110};
11141111
1112+ &pcie3_port0 {
1113+ reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
1114+ wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
1115+ };
1116+
11151117&pcie4 {
11161118 status = "okay";
11171119};
11241126};
11251127
11261128&pcie4_port0 {
1129+ reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
1130+ wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
1131+
11271132 wifi@0 {
11281133 compatible = "pci17cb,1107";
11291134 reg = <0x10000 0x0 0x0 0x0 0x0>;
11411146};
11421147
11431148&pcie6a {
1144- perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
1145- wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
1146-
11471149 vddpe-3v3-supply = <&vreg_nvme>;
11481150
11491151 pinctrl-0 = <&pcie6a_default>;
11591161 status = "okay";
11601162};
11611163
1164+ &pcie6a_port0 {
1165+ reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
1166+ wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
1167+ };
1168+
11621169&pm8550_gpios {
11631170 rtmr0_default: rtmr0-reset-n-active-state {
11641171 pins = "gpio10";
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