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pwm: mediatek: Add support for MT7981
The PWM unit on MT7981 uses different register offsets than previous MediaTek PWM units. Add support for these new offsets and add support for PWM on MT7981 which has 3 PWM channels, one of them is typically used for a temperature controlled fan. While at it, also reorder pwm_mediatek_of_data entries to restore alphabetic order. Signed-off-by: Daniel Golle <daniel@makrotopia.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
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1 file changed

Lines changed: 31 additions & 8 deletions

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drivers/pwm/pwm-mediatek.c

Lines changed: 31 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -38,6 +38,7 @@ struct pwm_mediatek_of_data {
3838
unsigned int num_pwms;
3939
bool pwm45_fixup;
4040
bool has_ck_26m_sel;
41+
const unsigned int *reg_offset;
4142
};
4243

4344
/**
@@ -59,10 +60,14 @@ struct pwm_mediatek_chip {
5960
const struct pwm_mediatek_of_data *soc;
6061
};
6162

62-
static const unsigned int pwm_mediatek_reg_offset[] = {
63+
static const unsigned int mtk_pwm_reg_offset_v1[] = {
6364
0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220
6465
};
6566

67+
static const unsigned int mtk_pwm_reg_offset_v2[] = {
68+
0x0080, 0x00c0, 0x0100, 0x0140, 0x0180, 0x01c0, 0x0200, 0x0240
69+
};
70+
6671
static inline struct pwm_mediatek_chip *
6772
to_pwm_mediatek_chip(struct pwm_chip *chip)
6873
{
@@ -111,7 +116,7 @@ static inline void pwm_mediatek_writel(struct pwm_mediatek_chip *chip,
111116
unsigned int num, unsigned int offset,
112117
u32 value)
113118
{
114-
writel(value, chip->regs + pwm_mediatek_reg_offset[num] + offset);
119+
writel(value, chip->regs + chip->soc->reg_offset[num] + offset);
115120
}
116121

117122
static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm,
@@ -285,60 +290,77 @@ static const struct pwm_mediatek_of_data mt2712_pwm_data = {
285290
.num_pwms = 8,
286291
.pwm45_fixup = false,
287292
.has_ck_26m_sel = false,
293+
.reg_offset = mtk_pwm_reg_offset_v1,
288294
};
289295

290296
static const struct pwm_mediatek_of_data mt6795_pwm_data = {
291297
.num_pwms = 7,
292298
.pwm45_fixup = false,
293299
.has_ck_26m_sel = false,
300+
.reg_offset = mtk_pwm_reg_offset_v1,
294301
};
295302

296303
static const struct pwm_mediatek_of_data mt7622_pwm_data = {
297304
.num_pwms = 6,
298305
.pwm45_fixup = false,
299306
.has_ck_26m_sel = true,
307+
.reg_offset = mtk_pwm_reg_offset_v1,
300308
};
301309

302310
static const struct pwm_mediatek_of_data mt7623_pwm_data = {
303311
.num_pwms = 5,
304312
.pwm45_fixup = true,
305313
.has_ck_26m_sel = false,
314+
.reg_offset = mtk_pwm_reg_offset_v1,
306315
};
307316

308317
static const struct pwm_mediatek_of_data mt7628_pwm_data = {
309318
.num_pwms = 4,
310319
.pwm45_fixup = true,
311320
.has_ck_26m_sel = false,
321+
.reg_offset = mtk_pwm_reg_offset_v1,
312322
};
313323

314324
static const struct pwm_mediatek_of_data mt7629_pwm_data = {
315325
.num_pwms = 1,
316326
.pwm45_fixup = false,
317327
.has_ck_26m_sel = false,
328+
.reg_offset = mtk_pwm_reg_offset_v1,
318329
};
319330

320-
static const struct pwm_mediatek_of_data mt8183_pwm_data = {
321-
.num_pwms = 4,
331+
static const struct pwm_mediatek_of_data mt7981_pwm_data = {
332+
.num_pwms = 3,
322333
.pwm45_fixup = false,
323334
.has_ck_26m_sel = true,
335+
.reg_offset = mtk_pwm_reg_offset_v2,
324336
};
325337

326-
static const struct pwm_mediatek_of_data mt8365_pwm_data = {
327-
.num_pwms = 3,
338+
static const struct pwm_mediatek_of_data mt7986_pwm_data = {
339+
.num_pwms = 2,
328340
.pwm45_fixup = false,
329341
.has_ck_26m_sel = true,
342+
.reg_offset = mtk_pwm_reg_offset_v1,
330343
};
331344

332-
static const struct pwm_mediatek_of_data mt7986_pwm_data = {
333-
.num_pwms = 2,
345+
static const struct pwm_mediatek_of_data mt8183_pwm_data = {
346+
.num_pwms = 4,
347+
.pwm45_fixup = false,
348+
.has_ck_26m_sel = true,
349+
.reg_offset = mtk_pwm_reg_offset_v1,
350+
};
351+
352+
static const struct pwm_mediatek_of_data mt8365_pwm_data = {
353+
.num_pwms = 3,
334354
.pwm45_fixup = false,
335355
.has_ck_26m_sel = true,
356+
.reg_offset = mtk_pwm_reg_offset_v1,
336357
};
337358

338359
static const struct pwm_mediatek_of_data mt8516_pwm_data = {
339360
.num_pwms = 5,
340361
.pwm45_fixup = false,
341362
.has_ck_26m_sel = true,
363+
.reg_offset = mtk_pwm_reg_offset_v1,
342364
};
343365

344366
static const struct of_device_id pwm_mediatek_of_match[] = {
@@ -348,6 +370,7 @@ static const struct of_device_id pwm_mediatek_of_match[] = {
348370
{ .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data },
349371
{ .compatible = "mediatek,mt7628-pwm", .data = &mt7628_pwm_data },
350372
{ .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data },
373+
{ .compatible = "mediatek,mt7981-pwm", .data = &mt7981_pwm_data },
351374
{ .compatible = "mediatek,mt7986-pwm", .data = &mt7986_pwm_data },
352375
{ .compatible = "mediatek,mt8183-pwm", .data = &mt8183_pwm_data },
353376
{ .compatible = "mediatek,mt8365-pwm", .data = &mt8365_pwm_data },

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