@@ -779,8 +779,8 @@ static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp)
779779
780780static int psr2_block_count_lines (struct intel_dp * intel_dp )
781781{
782- return intel_dp -> psr .io_wake_lines < 9 &&
783- intel_dp -> psr .fast_wake_lines < 9 ? 8 : 12 ;
782+ return intel_dp -> psr .alpm_parameters . io_wake_lines < 9 &&
783+ intel_dp -> psr .alpm_parameters . fast_wake_lines < 9 ? 8 : 12 ;
784784}
785785
786786static int psr2_block_count (struct intel_dp * intel_dp )
@@ -817,6 +817,7 @@ static void dg2_activate_panel_replay(struct intel_dp *intel_dp)
817817static void hsw_activate_psr2 (struct intel_dp * intel_dp )
818818{
819819 struct drm_i915_private * dev_priv = dp_to_i915 (intel_dp );
820+ struct intel_psr * psr = & intel_dp -> psr ;
820821 enum transcoder cpu_transcoder = intel_dp -> psr .transcoder ;
821822 u32 val = EDP_PSR2_ENABLE ;
822823 u32 psr_val = 0 ;
@@ -858,17 +859,18 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
858859 */
859860 int tmp ;
860861
861- tmp = map [intel_dp -> psr .io_wake_lines - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES ];
862+ tmp = map [psr -> alpm_parameters .io_wake_lines -
863+ TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES ];
862864 val |= TGL_EDP_PSR2_IO_BUFFER_WAKE (tmp + TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES );
863865
864- tmp = map [intel_dp -> psr .fast_wake_lines - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES ];
866+ tmp = map [psr -> alpm_parameters .fast_wake_lines - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES ];
865867 val |= TGL_EDP_PSR2_FAST_WAKE (tmp + TGL_EDP_PSR2_FAST_WAKE_MIN_LINES );
866868 } else if (DISPLAY_VER (dev_priv ) >= 12 ) {
867- val |= TGL_EDP_PSR2_IO_BUFFER_WAKE (intel_dp -> psr .io_wake_lines );
868- val |= TGL_EDP_PSR2_FAST_WAKE (intel_dp -> psr .fast_wake_lines );
869+ val |= TGL_EDP_PSR2_IO_BUFFER_WAKE (psr -> alpm_parameters .io_wake_lines );
870+ val |= TGL_EDP_PSR2_FAST_WAKE (psr -> alpm_parameters .fast_wake_lines );
869871 } else if (DISPLAY_VER (dev_priv ) >= 9 ) {
870- val |= EDP_PSR2_IO_BUFFER_WAKE (intel_dp -> psr .io_wake_lines );
871- val |= EDP_PSR2_FAST_WAKE (intel_dp -> psr .fast_wake_lines );
872+ val |= EDP_PSR2_IO_BUFFER_WAKE (psr -> alpm_parameters .io_wake_lines );
873+ val |= EDP_PSR2_FAST_WAKE (psr -> alpm_parameters .fast_wake_lines );
872874 }
873875
874876 if (intel_dp -> psr .req_psr2_sdp_prior_scanline )
@@ -1124,8 +1126,8 @@ static bool _compute_psr2_sdp_prior_scanline_indication(struct intel_dp *intel_d
11241126 return true;
11251127}
11261128
1127- static bool _compute_psr2_wake_times (struct intel_dp * intel_dp ,
1128- struct intel_crtc_state * crtc_state )
1129+ static bool _compute_alpm_params (struct intel_dp * intel_dp ,
1130+ struct intel_crtc_state * crtc_state )
11291131{
11301132 struct drm_i915_private * i915 = dp_to_i915 (intel_dp );
11311133 int io_wake_lines , io_wake_time , fast_wake_lines , fast_wake_time ;
@@ -1158,8 +1160,8 @@ static bool _compute_psr2_wake_times(struct intel_dp *intel_dp,
11581160 io_wake_lines = fast_wake_lines = max_wake_lines ;
11591161
11601162 /* According to Bspec lower limit should be set as 7 lines. */
1161- intel_dp -> psr .io_wake_lines = max (io_wake_lines , 7 );
1162- intel_dp -> psr .fast_wake_lines = max (fast_wake_lines , 7 );
1163+ intel_dp -> psr .alpm_parameters . io_wake_lines = max (io_wake_lines , 7 );
1164+ intel_dp -> psr .alpm_parameters . fast_wake_lines = max (fast_wake_lines , 7 );
11631165
11641166 return true;
11651167}
@@ -1291,7 +1293,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
12911293 return false;
12921294 }
12931295
1294- if (!_compute_psr2_wake_times (intel_dp , crtc_state )) {
1296+ if (!_compute_alpm_params (intel_dp , crtc_state )) {
12951297 drm_dbg_kms (& dev_priv -> drm ,
12961298 "PSR2 not enabled, Unable to use long enough wake times\n" );
12971299 return false;
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