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arm64: dts: renesas: r9a09g087: Add ICU support
The Renesas RZ/N2H (R9A09G087) SoC has an Interrupt Controller (ICU) block that routes external interrupts to the GIC's SPIs, with the ability of level-translation, and can also produce software and aggregate error interrupts. Add support for it. Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://patch.msgid.link/20251201112933.488801-5-cosmin-gabriel.tanislav.xa@renesas.com
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‎arch/arm64/boot/dts/renesas/r9a09g087.dtsi‎

Lines changed: 73 additions & 0 deletions
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@@ -759,6 +759,79 @@
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#power-domain-cells = <0>;
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};
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icu: interrupt-controller@802a0000 {
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compatible = "renesas,r9a09g087-icu", "renesas,r9a09g077-icu";
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reg = <0 0x802a0000 0 0x10000>,
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<0 0x812a0000 0 0x50>;
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#interrupt-cells = <2>;
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#address-cells = <0>;
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interrupt-controller;
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interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 1 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 2 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 3 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 4 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 5 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 6 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 7 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 8 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 9 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 10 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 11 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 12 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 13 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 14 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 15 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 16 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 17 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 18 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 20 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 22 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 23 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 25 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 26 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 27 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 28 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 29 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 31 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 406 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 407 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 408 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 409 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 410 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 411 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 412 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 413 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 414 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 415 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 416 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 417 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 418 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "intcpu0", "intcpu1", "intcpu2",
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"intcpu3", "intcpu4", "intcpu5",
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"intcpu6", "intcpu7", "intcpu8",
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"intcpu9", "intcpu10", "intcpu11",
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"intcpu12", "intcpu13", "intcpu14",
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"intcpu15",
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"irq0", "irq1", "irq2", "irq3",
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"irq4", "irq5", "irq6", "irq7",
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"irq8", "irq9", "irq10", "irq11",
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"irq12", "irq13", "irq14", "irq15",
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"sei",
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"ca55-err0", "ca55-err1",
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"cr520-err0", "cr520-err1",
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"cr521-err0", "cr521-err1",
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"peri-err0", "peri-err1",
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"dsmif-err0", "dsmif-err1",
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"encif-err0", "encif-err1";
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clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKM>;
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power-domains = <&cpg>;
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};
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pinctrl: pinctrl@802c0000 {
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compatible = "renesas,r9a09g087-pinctrl";
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reg = <0 0x802c0000 0 0x10000>,

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